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fifo
异步FIFO
输入: 16bit
输出:16bit
深度:256(Asynchronous FIFO
Input: 16bit
Output: 16bit
Depth: 256)
- 2017-07-10 14:02:36下载
- 积分：1
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3FP
一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)
- 2013-08-25 00:41:29下载
- 积分：1
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sgiarcs
ARC firmware interface defines.
- 2015-06-27 18:50:37下载
- 积分：1
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tlc549adc
FPGA AD数据采集模块，实现模拟信号到数字信号转换。(FPGA AD data acquisition module, the analog signal to digital signal conversion.)
- 2021-04-14 21:08:55下载
- 积分：1
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时钟同步的Verilog代码，signal_sync和crossdomain_signal
跨时钟同步功能的Verilog代码，有两个文件，signal_sync和crossdomain_signal
module signal_sync
(
clk_i,
rst_i,
signal_i,
signal_o,
valid_o,
edge_o,
posedge_o,
negedge_o
);
module crossdomain_signal (
input reset,
input clk_b,
input sig_domain_a,
output sig_domain_b
);
- 2022-02-02 17:04:15下载
- 积分：1
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Decodificador
System Verilog decodificator.
Enters a value(binary), drops hundreds, tens and units in BCD
- 2013-05-15 02:11:45下载
- 积分：1
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HT verilog 项目工程
rs232+HT verilog 门级网表代码，需Synopsys DC 综合
- 2022-08-16 23:06:52下载
- 积分：1
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fpga_sdram_inst
nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)
- 2013-08-24 22:26:31下载
- 积分：1
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cpsk_dpsk
数字通信系统相移键控CPSK信号和差分相移键控的调制与解调的VHDL代码(Phase shift keying digital communication system CPSK signals and differential phase-shift keying modulation and demodulation of the VHDL code for)
- 2009-11-06 16:11:03下载
- 积分：1
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decodeLogDomainSimple
When the initial input falls between the Switch off point and Switch on point values, the initial output is the value when the relay is off.
- 2017-01-29 18:04:53下载
- 积分：1
