登录
首页 » VHDL » 在SOPC Builder的UART IP核接口

在SOPC Builder的UART IP核接口

于 2022-03-04 发布 文件大小:109.01 kB
0 106
下载积分: 2 下载次数: 1

代码说明:

UART RS232 IPCORE for sopc builder -RS232 UART IPCORE for sopc builder

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • SV-Combinational-Logic
    system Verilog combinational logic
    2017-01-24 18:50:29下载
    积分:1
  • dianzhen(ok)
    驱动8*8点阵块显示汉字,可以自己根据要显示的内容随意更改,已通过验证。(Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.)
    2010-12-28 16:42:07下载
    积分:1
  • 很好的quartus软件仿真教程,flash版。
    很好的quartus软件仿真教程,flash版。-Good quartus software simulation tutorials, flash version.
    2023-03-08 19:40:06下载
    积分:1
  • Tutorial.tar
    zedboard partial reconfiguration tutorial
    2015-04-08 01:32:35下载
    积分:1
  • 14_SDRAM
    说明:  高速流水的SDRAM控制器,最高速度可达速度在200M左右(high speed SDRAM controller)
    2019-06-17 18:43:54下载
    积分:1
  • 8位相 加乘法器,具有高速,占用资源较少的优点
    8位相 加乘法器,具有高速,占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages
    2023-05-06 21:10:02下载
    积分:1
  • fjq1
    介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接 对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳 定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)
    2020-12-01 10:39:28下载
    积分:1
  • chenxu
    电子时钟,可以显示四位,两位显示分钟,两位显示秒,可以用按键控制清零,以及加减数(Electronic clock, you can display four bit, two bit display minutes, the second display seconds, can be used to control the key to clear, and the addition of subtraction)
    2017-04-22 21:29:14下载
    积分:1
  • 测试人体视觉的反应时间,可以作为vhdl编程的练习之用,也可以更进一步的开发成为具有商业价值的产品,这里面只是能够实现测试人体视觉反应时间的基本功能的程序...
    测试人体视觉的反应时间,可以作为vhdl编程的练习之用,也可以更进一步的开发成为具有商业价值的产品,这里面只是能够实现测试人体视觉反应时间的基本功能的程序-Test of human visual reaction time, can be used as VHDL programming exercises used can also be further developed into products with commercial value, there is only able to realize the human visual reaction time test the basic functions of the procedures
    2022-10-07 16:40:02下载
    积分:1
  • 改变盒FPGA DE2
    Alter kit FPGA de2-35 This project shows a cascade motion through board leds.-Alter kit FPGA de2-35 This project shows a cascade motion through board leds.
    2022-03-06 03:51:32下载
    积分:1
  • 696518资源总数
  • 105547会员总数
  • 4今日下载