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IIR
使用verilog语言描述的二阶巴特沃斯IIR滤波器，程序中有参数说明，已经运行通过(Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter description has been run through)
- 2013-06-18 16:30:35下载
- 积分：1
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SHIFT_8REG是8位的一个具有移位功能的寄存器，每一次数据打入都会从这个寄存器的最低位打入，并相应进行向左移位。
ODD_110BREG是一个3位的备...
SHIFT_8REG是8位的一个具有移位功能的寄存器，每一次数据打入都会从这个寄存器的最低位打入，并相应进行向左移位。
ODD_110BREG是一个3位的备份寄存器，寄存器中存放的是奇数帧的同步头，也就是110。
EVEN_9BHREG是一个8位的备份寄存器，寄存器中存放的是偶数帧的同步头，也就是10011011。这两个寄存器的初始值在系统一开始就打入。
-SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register is stored in the odd frame synchronization head, is 110. EVEN_9BHREG 8 is a backup Register, which register is kept even the first frame synchronization, is 10011011. This register the two initial value of the system into a start.
- 2022-05-15 03:11:22下载
- 积分：1
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伪随机二进制序列无符号17位计数器
这通过反馈来实现一个 17 位伪随机的无符号计数器异或的位 0 和 3。 注意 ︰ 如果也绝不是独家使用相反，这会反相平行的位模式 & 这将意味着所有位都零是一种有效模式和所有那些不都是有效。 目前所有的都是有效的。
- 2022-12-08 06:25:03下载
- 积分：1
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SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序
SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序-SONY company produced black-and-white CCD (44 megapixels) ICX229 the drive signal generation process
- 2022-04-17 08:51:11下载
- 积分：1
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This tutorial presents an introduction to Altera’s Nios R
II processor, which...
This tutorial presents an introduction to Altera’s Nios R
II processor, which is a soft processor that can be in-
stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.
- 2023-06-21 11:25:02下载
- 积分：1
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transmittermegafunction
lvds transmitter megafunction (lvds transmitter megafunction)
- 2008-03-09 19:40:03下载
- 积分：1
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xilinx provided on the FPGA hardware design timing constraints of the amount of...
xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material
- 2023-06-26 19:00:04下载
- 积分：1
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VESA Timing
VESA CVT视频参数计算器，输入分辨率和刷新率即可得到需要参数。(VGA Timing Calculator)
- 2020-12-23 14:29:07下载
- 积分：1
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fifo16_16
异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)
- 2020-10-26 10:49:59下载
- 积分：1
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本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!
本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!
- 2022-03-01 07:15:01下载
- 积分：1
