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CNTRTEST3_7tx_rx_0422
在ISE12.4与TMS320F2812的XINTF接口，实现数据收发(In ISE12.4 TMS320F2812 the XINTF, data transceiver)
- 2021-01-08 10:48:51下载
- 积分：1
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forwarding
浙江大学体系结构实验课代码，5级流水线实现旁路和停顿(5-stage pipeline to achieve realization of the bypass pipeline bypass pause 5 pause)
- 2020-09-26 12:07:46下载
- 积分：1
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can-lite-vhdl-master
CAN VHDL Code. Behavioral implementation of CAN bus interface.
- 2021-01-19 21:48:41下载
- 积分：1
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class17_TLC5620
TLC5620驱动程序包括其他文件,8位，4通道，电压输出型DAC的数模转换器(TLC5620 driver and doc)
- 2018-08-13 16:58:54下载
- 积分：1
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altfp_matrix_mult
浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)
- 2013-12-18 15:08:36下载
- 积分：1
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alu
verilog code for 8 bit alu
- 2015-06-30 18:49:10下载
- 积分：1
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dds
dds叫数字频率合成计，是一种在FPGA广泛使用的信号生成方式，根据频率可控，比一般的信号优点很多。
- 2023-07-28 03:40:03下载
- 积分：1
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weitb
在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。(In digital communication, usually from receiving directly in digital signal extracted a synchronized signal, the direct method according to the extraction synchronized signal way, can be roughly divided into filtering method and phase lock method. Phase lock method is using of phase locked loop to extract a synchronized signal method, the design scheme is based on phase locked loop of a synchronous extraction method and can be quickly extract a synchronous clock, and design simple, convenient modification parameter. The Quartus II design software of the system, and the simulation test Altera Cyclone II FPGA chip to achieve Ep2c5 series.)
- 2020-12-01 10:39:28下载
- 积分：1
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uart_slip
实现串口通讯以及SLIP协议传输数据，增加了特殊字符的转义(Realization of Serial Communication and SLIP Protocol)
- 2021-01-19 18:58:41下载
- 积分：1
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flash_test_24
实现fpga 读写flash 在k7上验证(Realization of FPGA read-write flash verification on K7)
- 2020-06-18 20:00:02下载
- 积分：1
