登录
首页 » VHDL » 用verilog hdl 硬件描述语言写的一个范例程序,led的,扩展性极强,欢迎大家下载使用。...

用verilog hdl 硬件描述语言写的一个范例程序,led的,扩展性极强,欢迎大家下载使用。...

于 2022-03-06 发布 文件大小:1.05 kB
0 45
下载积分: 2 下载次数: 1

代码说明:

用verilog hdl 硬件描述语言写的一个范例程序,led的,扩展性极强,欢迎大家下载使用。-Verilog hdl using hardware description language to write an example of the procedure, led, and highly scalable, welcome to download.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 1
    说明:  matlab code for JTAG cable checking
    2014-02-04 19:27:39下载
    积分:1
  • rc-evga-indtube
    evga-indtube.h - Keytable for evga_indtube Remote Controller.
    2015-04-16 11:06:12下载
    积分:1
  • vhdl学习方法,含有大量的vhdl源代码,对vhdl的语法的介绍
    vhdl学习方法,含有大量的vhdl源代码,对vhdl的语法的介绍-VHDL source习laugh Yang, Yi bleed at the nose cavity submerged stresses measured tungsten Daitou VHDL, VHDL-Qin Pang Yang cavity cavity Geng Zhuang
    2023-07-17 16:40:03下载
    积分:1
  • 234
    在接收信号的数字化、软化的实现中,数字下变频起着重要的作用。本文首先介绍了数字下 变频的组成结构,然后详细分析了数字下变频的工作原理,描述了在实现数字下变频时,设计方案所 采用的高效滤波器———CIC 滤波器和多相抽取滤波器的结构和原理。最后,用通过Simulink 对数字 下变频的性能进行了仿真。在仿真的基础上使用Insight 公司的FPGA 开发系统,用测试电路实测了 数字下变频的性(In the receiving digital signal, softening the realization, the digital down-conversion plays an important role. This article first introduced the digital down conversion of the composition, and then a detailed analysis of digital down conversion of the working principle described in the realization of digital down conversion, the design used in high-performance filters--- CIC filters and multi-phase extraction filter structure and principle. Finally, with the adoption of Simulink for digital down-conversion performance of the simulation. In the simulation based on the use of Insight s FPGA development system is measured using the test circuit of the digital down-conversion of)
    2021-03-16 21:29:21下载
    积分:1
  • 这是FPGA的Spartan 3E基础工程文件。该项目是基于VGA游戏…
    this fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.
    2023-02-25 10:20:03下载
    积分:1
  • AlteraFPGA_CPLD
    ALTERA FPGA CLPD
    2010-04-11 14:52:36下载
    积分:1
  • fftip
    2008-2009年优秀硕士论文之:基于FPGA的高性能32位浮点FFT IP核的开发(Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development)
    2010-12-09 19:31:46下载
    积分:1
  • 国外的VHDL应用例子,大家可一好好参考一下!
    国外的VHDL应用例子,大家可一好好参考一下!-abroad VHDL Application examples, we can make reference to a properly!
    2022-01-25 20:56:43下载
    积分:1
  • DDR SDRAM控制器的VHDL代码
    DDR SDRAM控制器的VHDL代码已经测试-DDR SDRAM controller VHDL code
    2022-02-24 20:41:05下载
    积分:1
  • 实用的程序代码,希望对大家有用,已经调试通过
    实用的程序代码,希望对大家有用,已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through
    2022-06-03 06:28:25下载
    积分:1
  • 696524资源总数
  • 103938会员总数
  • 55今日下载