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m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...
m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
- 2022-02-02 08:36:01下载
- 积分:1
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一款verilog设计的SRAM控制器svtb_ahb_sram
一款verilog设计的SRAM控制器,可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)
- 2020-06-30 13:40:02下载
- 积分:1
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fpalign_struct
floating point alignment
- 2013-03-11 16:53:31下载
- 积分:1
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fir滤波器,Verilog语言写的,容易看懂
fir滤波器,Verilog语言写的,容易看懂-fir filter, Verilog language written in easy to understand
- 2023-03-26 01:30:04下载
- 积分:1
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语音采集,直接在QUARTUSII中打开调试.
语音采集,直接在QUARTUSII中打开调试.-err
- 2022-01-22 11:44:02下载
- 积分:1
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用于fpga学习,共同分享学习经验和交流学习心得
用于fpga学习,共同分享学习经验和交流学习心得-For fpga to learn, to share learning experiences and the exchange of learning
- 2022-02-25 22:21:38下载
- 积分:1
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我是VHDL的初学者,这是我自己编译的简单的几个VHDL码,功能有3...
我是VHDL的初学者,这是我自己编译的简单的几个VHDL码,功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。
希望能和其他初学者一起讨论学习,并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3-8 function decoder and testbench, 16 Register and testbench and traffic lights. Hopes to be able to discuss other beginners learning, and with the guidance of the master
- 2022-05-14 07:13:44下载
- 积分:1
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float_mult32x32.v
verilog 语言写的FPGA内部实现硬件浮点乘法器的源码,两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)
- 2018-07-19 17:33:42下载
- 积分:1
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8051MCU in the FPGA to achieve the source code, using VHDL language
8051MCU在FPGA上实现的源代码,用VHDL语言编写-8051MCU in the FPGA to achieve the source code, using VHDL language
- 2022-02-22 06:28:53下载
- 积分:1
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页面置换算法中的三种算法相关程序代码
FIFO LUR OPT
页面置换算法中的三种算法相关程序代码
FIFO LUR OPT-yemianzhihuansuanfa
- 2022-10-19 08:10:03下载
- 积分:1