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spi_ad
FPGA与DAC芯片的SPI接口驱动，实现串行数据的传输。(Realizing the communication between FPGA and DA chip)
- 2017-06-23 12:38:22下载
- 积分：1
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fwwallace
wallace tree multiplier in verrilog
- 2013-03-19 00:15:07下载
- 积分：1
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AD4003_CTR
一个AD4003的测试/控制程序，2Ms/s，18bit的AD高速AD芯片(A AD4003 test / control program, 2Ms/s, 18bit AD high speed AD chip)
- 2020-08-24 08:18:16下载
- 积分：1
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数字信号处理的FPGA实现-第三版-verilog源程序
数字信号处理的FPGA实现, 包括了FPGA基础知识，浮点运算，信号处理的FIR FFT等，附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)
- 2017-08-06 17:38:33下载
- 积分：1
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demo_as32ttl1w
可以获取各种字符，并在数码管显示出来，非常的靠谱且稳定(Various characters can be acquired and displayed on the digital tube.)
- 2020-06-16 15:00:02下载
- 积分：1
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讲解快速傅里叶变换
讲解快速傅里叶变换--FFT快速算法的文章。-On Fast Fourier Transform- FFT fast algorithm for the article.
- 2022-06-01 02:12:26下载
- 积分：1
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sdram-control-verilog
SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.)
- 2009-12-11 15:01:46下载
- 积分：1
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减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制...
减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d
- 2022-01-28 03:17:59下载
- 积分：1
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The experimental results are used to prepare MOSIN6 is achieved Verilog HDL lang...
有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的.
练习三 利用条件语句实现计数分频时序电路
实验目的：
1. 掌握条件语句在简单时序模块设计中的使用；
2. 学习在Verilog模块中应用计数器；
3. 学习测试模块的编写、综合和不同层次的仿真。
练习四 阻塞赋值与非阻塞赋值的区别
实验目的：
1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别；
2． 了解阻塞赋值与非阻塞赋值的不同使用场合；
3． 学习测试模块的编写、综合和不同层次的仿真。
-The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment usi
- 2022-03-18 15:26:04下载
- 积分：1
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基于fpga和xinlinx ise的串行通信vhdl程序，希望对你有所帮助！
基于fpga和xinlinx ise的串行通信vhdl程序，希望对你有所帮助！-xinlinx and ideally serial communications VHDL process, and I hope to help you!
- 2023-05-29 05:45:03下载
- 积分：1
