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pinlvji
用汇编语言设计的频率计，注释较详细，适于初学者学习使用(Assembly language design frequency meter, the comment in more detail, suitable for beginners to learn to use)
- 2012-04-16 10:47:59下载
- 积分：1
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FPGA中实现的硬件UDP 协议
FPGA中实现的硬件UDP 协议 FPGA中实现的硬件UDP 协议
- 2022-03-23 19:25:50下载
- 积分：1
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using VHDL prepared by the LED display driver circuit design source
用VHDL语言编写的LED显示器驱动电路的设计源程序-using VHDL prepared by the LED display driver circuit design source
- 2023-07-22 14:55:03下载
- 积分：1
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VHDL——如何写简单的testbench
基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)
- 2017-07-31 15:00:45下载
- 积分：1
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Booth2_final
该文件是booth乘法器的verilog源代码，经过最终的仿真，可以直接运行(This file is booth multiplier verilog code, after the final simulation, can be directly run)
- 2015-05-08 09:29:56下载
- 积分：1
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ComChange-12061629
说明： 并行读写14路串口数据，数据被写入FIFO，在收到读写信号后，SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)
- 2019-03-13 01:38:44下载
- 积分：1
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FPGA
基于FPGA的FFT处理器的实现，适合做fpga的工程技术人员参考-FPGA-based realization of the FFT processor, suitable for the engineering and technical personnel fpga reference
- 2022-09-26 01:05:03下载
- 积分：1
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高阶矩阵奇异值分解的FPGA实现方法svd_fpga
一种计算高阶矩阵奇异值分解的FPGA实现方法。(A high-end computing matrix singular value decomposition of the FPGA realization method.)
- 2020-07-07 12:28:57下载
- 积分：1
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本源码详细介绍了UART的经典实例，敬请下载，谢谢适用
本源码详细介绍了UART的经典实例，敬请下载，谢谢适用-The source described in detail a classic example of UART, please download, Thank you apply
- 2022-03-22 20:09:19下载
- 积分：1
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costas
costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块(costas the verilog program, including multipliers, DDS, phase detector, loop filter modules)
- 2011-08-19 10:20:53下载
- 积分：1
