登录
首页 » VHDL » 各种加法器的 vhdl 代码

各种加法器的 vhdl 代码

于 2022-03-07 发布 文件大小:3.29 kB
0 50
下载积分: 2 下载次数: 1

代码说明:

下面是各种文件,有 vhdl 代码和进位保留加法器的验证平台,进行超前进位加法器,等等。综合和代码已经模拟了。 给出的所有加法器是 16 位加法器,并实施新思科技。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • jpeg_fpga
    基于FPGA的JPEG解码,对开发图片解码的人有用。(FPGA-based JPEG decoding, the development of image decoding useful.)
    2014-02-24 09:19:22下载
    积分:1
  • alu
    说明:  VHDL实现的算术逻辑计算单元(ALU),包括modersim测试文件,即仿真结果。(VHDL implementation of the arithmetic logic calculation unit (ALU), including modersim test file, the simulation results.)
    2011-03-26 21:18:01下载
    积分:1
  • DDA_xy
    说明:  运用Verilog 语言进行数字积分法,将X轴和Y轴进行插补运算。(Verilog language using digital integration method, the X axis and Y axis interpolation operations.)
    2020-11-27 18:19:30下载
    积分:1
  • Verilog语法
    说明:  Verilog语法教程,适合初学者,详细(Verilog instruction book)
    2019-05-04 16:07:18下载
    积分:1
  • usb 硬件实现 请大家多多指教
    usb 硬件实现 请大家多多指教-usb hardware realize the exhibitions please everyone
    2022-01-28 13:02:47下载
    积分:1
  • 键盘输入液晶模块显示字符,在液晶显示屏上显示从PS2键盘输入的字符...
    键盘输入液晶模块显示字符,在液晶显示屏上显示从PS2键盘输入的字符-Keyboard input LCD display module characters displayed in the LCD screen from the PS2 keyboard input characters
    2022-10-02 08:20:03下载
    积分:1
  • pingpang_ram
    乒乓RAM静态随机存储器的控制,用于解决数据流连续存储问题。(Ping pong RAM static random access control, to solve the problem of continuous data flow storage.)
    2020-09-22 10:17:50下载
    积分:1
  • BmpDecoder
    适用于Altera FPGA Nios II平台uClinux OpenCV之BmpDecoder的源码(Souce code of BmpDecoder for Altera FPGA Nios II uClinux OpenCV)
    2011-02-11 16:43:45下载
    积分:1
  • jesd204_0_ex
    jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)
    2020-11-26 14:49:31下载
    积分:1
  • TOFED_TB_1
    A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition diagram, a state table and a schematic for your circuit. Design an alternate implementation using just three flip flops and draw a state transition diagram, state table and a schematic for your circuit. If your designs are extended to implement an n bit twisted ring counter, how many flip flops are required using each of the two approaches. In what situations would you prefer the first method? In what situations would you prefer the second?
    2014-11-08 06:58:55下载
    积分:1
  • 696522资源总数
  • 104029会员总数
  • 31今日下载