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fpga--lpass
基于FPGA的数字低通滤波器 。。。。。(FPGA-based digital low-pass filter。。。。。)
- 2021-04-24 08:28:47下载
- 积分：1
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7 digital display decoder design 7 Digital is pure combinational circuits, usual...
7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
- 2022-08-11 21:55:01下载
- 积分：1
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adc_cfg
adc器件ads62p49配置代码，已在工程中验证可用(Temperature sensor DS18B20 parses the code, has verified the ADC device configuration code, has been verified available)
- 2020-11-04 16:29:51下载
- 积分：1
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verilog写的数字频率计的显示模块,可以
verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be
- 2022-03-23 18:10:33下载
- 积分：1
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基于NiosⅡ的2 de2_tvproject
本演示使用VGA输出和DVD播放器播放视频和音频输入
- 2022-01-26 03:44:01下载
- 积分：1
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K9HCG08U1D K9PDG08U5D K9LBG08U0D K9MDG08U5D 三星 4G 8G 16G nand资料
K9HCG08U1D K9PDG08U5D K9LBG08U0D K9MDG08U5D 三星 4G 8G 16G nand资料-K9HCG08U1D K9PDG08U5D K9LBG08U0D K9MDG08U5D Samsung 4G 8G 16G nand datasheet
- 2022-01-28 16:21:35下载
- 积分：1
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手机号码归属地查询,代码详尽，简单易懂，欢迎使用！
手机号码归属地查询,代码详尽，简单易懂，欢迎使用！-hello!welcome to my code !thank you !
- 2022-01-27 16:05:17下载
- 积分：1
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ad5791
在Quartus环境下编写，使用Cyclong系列芯片，配置七通道高精度AD5791，该例子为AD5791的FPGA配置使能代码,包括模拟数据输入模块，复位模块，命令接收是能配置模块。(AD5781，Digital signal convert to Analog signal)
- 2021-04-20 14:28:50下载
- 积分：1
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test2
说明： 试用Verilog HDL语言，设计十进制计数器，将计数过程用一个数码管进行显示（0～9）。要求首先使用Modelsim软件进行功能仿真，然后使用Quartus软件综合，并下载到开发板进行电路功能测试。(Using Verilog HDL language, a decimal counter is designed. The counting process is displayed by a digital tube (0 ~ 9). It is required to first use Modelsim software for functional simulation, then use quartus software for synthesis, and download to the development board for circuit functional test.)
- 2020-05-17 11:07:28下载
- 积分：1
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hanming
Verilog HDL语言编写的汉明编码及解码器，附有时序仿真文件(Verilog HDL language encoding and decoding Hamming, with timing simulation file)
- 2017-06-22 15:56:38下载
- 积分：1
