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数字频率计 FPGA 用verilog语言编写
数字频率计 FPGA 用verilog语言编写-Digital Cymometer verilog language used FPGA
- 2023-01-25 21:10:03下载
- 积分:1
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led1
说明: 点亮led流水灯,通过调用锁相环,可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)
- 2020-06-16 07:00:01下载
- 积分:1
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ALU vhdl
此模块模拟alu(算术逻辑单元)和测试台,以验证其工作是否正确。
- 2023-08-23 08:20:04下载
- 积分:1
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VHDL开发的计数器。源程序不复杂,应该都能看懂。最重要的注意:是时序问题
VHDL开发的计数器。源程序不复杂,应该都能看懂。最重要的注意:是时序问题-VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue
- 2022-05-14 00:07:18下载
- 积分:1
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EEPROM_RD_WR
本程序包含:EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块(eeprom_wr.v)、信号产生模块(signal.v)和顶层模块(top.v) ,这样可以有一个完整的EEPROM的控制模块和测试文件,本文件通过测试。(This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (eeprom_wr.v), signal generator module (signal.v) and top-level module (top.v), this can have a EEPROM complete control module and test document, this document is to pass the test.)
- 2008-12-23 15:04:20下载
- 积分:1
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RDA1846
rda1846 + pic18f2552 usb circuit schematic.
- 2012-09-12 20:05:38下载
- 积分:1
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add4bit
一位全加器的VHDL源码与TEST BENCH.XILINX下通过(A full adder and the VHDL source code through TEST BENCH.XILINX)
- 2009-07-20 08:18:37下载
- 积分:1
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fftip
2008-2009年优秀硕士论文之:基于FPGA的高性能32位浮点FFT IP核的开发(Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development)
- 2010-12-09 19:31:46下载
- 积分:1
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0
说明: 用VHDL语言设计一个校验器,用for loop实现8位数据的偶校验,(With a for loop to achieve 8-bit data parity)
- 2011-12-06 15:47:01下载
- 积分:1
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VHDL编写的4个led灯循环明暗变化,通过改变波形占空比实现,课堂作业自编程序...
VHDL编写的4个led灯循环明暗变化,通过改变波形占空比实现,课堂作业自编程序-VHDL prepared by the four led lights cycle shading changes, by changing the waveform duty cycle to achieve, self-compiled class operating procedures
- 2022-04-17 17:16:20下载
- 积分:1