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ALTERA嵌入式设计大赛获奖作品文章，非常适合DE2开发参考
ALTERA嵌入式设计大赛获奖作品文章，非常适合DE2开发参考-ALTERA Embedded Design Competition Prize-winning article, very suitable for the development of reference DE2
- 2022-04-07 11:00:16下载
- 积分：1
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fpga VHDL语言，控制DDS产生频率可变的正弦波信号扫频
fpga VHDL语言，控制DDS产生频率可变的正弦波信号扫频-FPGA VHDL DDS
- 2022-06-29 15:53:56下载
- 积分：1
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gg
说明： FPGA实现基带成型滤波器，升余弦滚降系数，多进制调制(FPGA)
- 2010-12-20 17:55:18下载
- 积分：1
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16x2液晶显示驱动设计的FPGA。
16X2液晶显示屏的FPGA显示驱动设计。-16x2 LCD display driver design of the FPGA.
- 2022-02-27 02:16:22下载
- 积分：1
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eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
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- 2021-03-07 15:49:29下载
- 积分：1
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TFT_CTRL_800_480_16bit
文件用于驱动TFT屏，分辨率800*400，平台为quartus13，芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)
- 2019-04-12 09:22:29下载
- 积分：1
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12232-LCD
12232型号LCD液晶屏显示程序，简单易懂(12232 Model LCD screen display program, easy to understand)
- 2013-06-09 10:26:27下载
- 积分：1
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VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling
VHDL Code For Full Adder By Data Flow Modelling
- 2013-11-08 00:39:04下载
- 积分：1
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本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。...
本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.
- 2022-07-20 09:46:32下载
- 积分：1
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VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用
VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用-CARDBUS IP CORE
- 2022-03-12 11:28:40下载
- 积分：1
