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How to control the time s equence of LM3033B
讨论如何利用软件控制 !"#$## &$ ’# 液晶显示模块时序(采用 )*+ 语言编程(驱动
液晶模块实现并行传输方式的字符#汉字以及图形显示$具体阐述了 !"#$## !$ ’# 液晶显示
模块与单片机 ,-./0*1 的并行接口电路和软件编程方法$
关键词"!"#$## &$ ’# 液晶显示模块 0-2/1$ 控制器 ,-./0*1 单片机 )*+ 编程-How to control the time s equence of LM3033B- 0BR3 LCD module by C51
programming was dis cus s ed in this paper. In this way the LCD module was driven by
parallel communication and the characters and graphics could be displayed well. The parallel
interface circuit and the soft des ign between LM3033B- 0BR3 LCD module and AT89S52
were narrated in detail.
- 2022-03-21 07:54:47下载
- 积分：1
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QPSK的生成的程序，很简单！是在MATLAB中运行的
QPSK的生成的程序，很简单！是在MATLAB中运行的-QPSK generation procedure is very simple! Is running in the MATLAB
- 2023-09-07 13:30:02下载
- 积分：1
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C algorithms for realtime Digital Signal Processors
C algorithms for realtime Digital Signal Processors
- 2022-06-13 04:16:51下载
- 积分：1
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本书详细介绍了c++的技术，为中高级程序员使用，是一本内容丰富，很有深度的国际标准书籍...
本书详细介绍了c++的技术，为中高级程序员使用，是一本内容丰富，很有深度的国际标准书籍-Described in detail in this book c++ of the technology, the use of senior programmers, are rich in content and a very deep book of international standards
- 2022-05-31 09:11:18下载
- 积分：1
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Wily
老谋深算―〈孙子兵法〉启示录
学习孙子兵法！
大家看啊看！
尽管下载！
有好东西，大家分享！-Wily-
- 2022-06-13 00:34:45下载
- 积分：1
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是一本系统讲解相控阵雷达数据处理的好书。主编：蔡庆宇
是一本系统讲解相控阵雷达数据处理的好书。主编：蔡庆宇-Is a system on Phased Array Radar Data Processing books. Editor-in-Chief:蔡庆宇
- 2022-12-22 17:35:03下载
- 积分：1
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powerpcb软件应用高级技巧，深入学习powerpcb技巧
powerpcb软件应用高级技巧，深入学习powerpcb技巧-Advanced powerpcb software application skills, in-depth study skills powerpcb
- 2022-08-21 06:10:57下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
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基于WinCE平台的开发指南。详细介绍了系统的启动、配置等信息。...
基于WinCE平台的开发指南。详细介绍了系统的启动、配置等信息。-The development of guidelines based on the WinCE platform. Details of the system startup, configuration and other information.
- 2023-07-16 08:35:05下载
- 积分：1
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DLL编程指导,讲的很全面
DLL编程指导,讲的很全面-DLL programming guide, for the very comprehensive
- 2022-07-08 12:00:51下载
- 积分：1
