登录
首页 » VHDL » 这是一个控制芯片CPLD 1394的verilog程序,可以参考应用。

这是一个控制芯片CPLD 1394的verilog程序,可以参考应用。

于 2022-03-11 发布 文件大小:3.32 kB
0 124
下载积分: 2 下载次数: 1

代码说明:

这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.-This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • cordic
    cordic算法,实现加减乘除、幂次方、开方的运算(CORDIC algorithm implementation, power add, subtract, multiply and divide and square root operations)
    2020-06-29 14:00:01下载
    积分:1
  • VHDL USB2.0接口源码,内有说明,详细.
    VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.
    2022-04-29 19:53:42下载
    积分:1
  • 一三FFT变换(头:这是一个代码3)
    fft变换三个中的一个(站长:三个代码算一个)-fft transformation of a three (head : It is a code 3)
    2022-08-10 18:57:06下载
    积分:1
  • unit5
    低频数字式相位测量仪 使用的VHDL语言,在MUXPLUS2环境下使用! (digit hpase detecter use for low-frequence)
    2010-05-07 17:00:35下载
    积分:1
  • NEW
    Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭,按开始键后,数码管显示全为0。输入一定数额,数码管显示该数额的两倍对应的时间,按确认后开始倒计时。输入数额最多为20。若10秒没有按键,数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)
    2020-12-10 16:29:20下载
    积分:1
  • jiaotongdeng
    数字电路课程设计,用VHDL实现交通灯的控制(Digital circuit design using VHDL control of traffic lights)
    2014-06-16 18:26:53下载
    积分:1
  • 一个用vhdl硬件描述语言实现的一个比较简单的除法器
    一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl
    2022-05-15 11:56:12下载
    积分:1
  • This tutorial presents an introduction to Altera’s Nios R II processor, which...
    This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.
    2023-06-21 11:25:02下载
    积分:1
  • rotary
    Spartan 3E上的Rotary encoder控制程序,及验证它的小灯程序(Rotary encoder on the Spartan 3E control procedures, and verification procedures for its small light)
    2010-11-27 01:40:13下载
    积分:1
  • Program to implement convolution of two signals.
    Program to implement convolution of two signals.
    2023-04-30 22:25:04下载
    积分:1
  • 696518资源总数
  • 105547会员总数
  • 4今日下载