-
To increase simulation speed, ModelSim® can apply a variety of optimizations...
To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
- 2022-03-06 09:05:21下载
- 积分：1
-
STDL80
Leonardo综合器用STDL80 0.5um综合库，安装见说明，找到它真不容易。(STDL80 0.5um ASIC Library for Leonardo)
- 2015-03-14 10:29:12下载
- 积分：1
-
一个完整的设计DE2_project,希望对大家有所帮助，谢谢ok
一个完整的设计DE2_project,希望对大家有所帮助，谢谢ok-A complete design DE2_project, everyone would like to be helpful, thank you ok
- 2022-04-18 05:42:24下载
- 积分：1
-
srio
fpga平台实现srio通信，以及srio端口寄存器设计。(FPGA platform to achieve sRIO communication, as well as sRIO port register design.)
- 2017-07-09 16:52:45下载
- 积分：1
-
篮球24s计时器，元器件简单，功能复杂。满足小型计时需要。...
篮球24s计时器，元器件简单，功能复杂。满足小型计时需要。
- 2022-05-30 17:01:58下载
- 积分：1
-
FPGA和DSP EMIFA口接口程序。在两FPGA分布
FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.
- 2023-01-25 08:30:04下载
- 积分：1
-
fffffff
如上图所示， Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
(As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2020-11-04 20:39:51下载
- 积分：1
-
ROM模块，功能在于，是创建一个简易的rom模块
ROM模块，功能在于，是创建一个简易的rom模块-rom
- 2022-03-31 16:48:46下载
- 积分：1
-
AES-on-FPGA
AES算法在FPGA上的实现，对AES算法所用的器件资源进行了总结(AES on FPGA the Fastest to the Smallest)
- 2014-12-31 10:06:46下载
- 积分：1
-
verilog-lfsr-master
说明： Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.
- 2020-06-24 21:40:01下载
- 积分：1
