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altera_reed_solomon_design
altera 的reed solomn 设计(reed solomn design from altera)
- 2009-06-14 15:39:32下载
- 积分：1
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FPGA
fpga 设计全攻略，很好的fpga入门提高资料(the fpga design Raiders, good fpga the Getting Started improve data)
- 2012-12-09 19:03:23下载
- 积分：1
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测试VANET应用程序
他延误用户inrandom经历过或基于竞争的MAC方案是无界;用户可能需要等待论坛很长一段时间，直到他/她发送一些数据的机会。在otherhand，通过根据一定的deterministicpattern，这被称为由梅西和马特仕协议序列调度所述数据分组，延迟的hardguarantee可以完成。
- 2022-07-10 10:09:43下载
- 积分：1
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fjq1
介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳
定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)
- 2020-12-01 10:39:28下载
- 积分：1
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FFT
使用VHDL语言实现对快速傅立叶变换算法的实现，并通过仿真验证其正确性。(Using VHDL language implementation for the realization of fast Fourier transform algorithm, and its correctness is validated by computer simulation.)
- 2021-04-03 21:49:05下载
- 积分：1
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Lossless_Compression_Method_for_Bayer_Image_and_FP
描述Bayer图像无损压缩的一种先进算法及其如何在FPGA上实现(Description Bayer Image is an advanced lossless compression algorithms in the FPGA to achieve and how)
- 2010-08-31 12:24:49下载
- 积分：1
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clz
说明： 对于一串二进制数前置零的计数的Verilog程序(For a string of binary zero count Verilog pre-procedure)
- 2021-03-31 21:29:08下载
- 积分：1
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CameraLink_Oserdes2_test
40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )
- 2014-02-25 14:06:38下载
- 积分：1
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Tutorijal 6
说明： Ovo sto saljem je tutorijal 7 sa vhdlom
- 2018-12-22 06:47:31下载
- 积分：1
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使用vhdl语言实现对led的控制，还有电路仿真
使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation
- 2022-03-12 11:40:55下载
- 积分：1
