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在接收信号的数字化、软化的实现中,数字下变频起着重要的作用。本文首先介绍了数字下
变频的组成结构,然后详细分析了数字下变频的工作原理,描述了在实现数字下变频时,设计方案所
采用的高效滤波器———CIC 滤波器和多相抽取滤波器的结构和原理。最后,用通过Simulink 对数字
下变频的性能进行了仿真。在仿真的基础上使用Insight 公司的FPGA 开发系统,用测试电路实测了
数字下变频的性(In the receiving digital signal, softening the realization, the digital down-conversion plays an important role. This article first introduced the digital down conversion of the composition, and then a detailed analysis of digital down conversion of the working principle described in the realization of digital down conversion, the design used in high-performance filters--- CIC filters and multi-phase extraction filter structure and principle. Finally, with the adoption of Simulink for digital down-conversion performance of the simulation. In the simulation based on the use of Insight s FPGA development system is measured using the test circuit of the digital down-conversion of)
- 2021-03-16 21:29:21下载
- 积分:1
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Bayer2RGB
Bayer 转RGB Verilog代码实现。。5*5 窗口。在工程中应用的(Bayer to RGB Verilog code implementation. 5*5 window. Applied in Engineering)
- 2020-12-14 15:29:15下载
- 积分:1
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10进制的FPGA数字计数器
本程序可以在DE1-SOC的实现10进制的FPGA数字计数器
- 2023-07-19 19:25:05下载
- 积分:1
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MIPS32五级流水线CPU Verilog代码,注释清晰,供学习
应用背景
Verilog 实现 MIPS32 V1整数指令集, 5级流水线CPU
没有文档,按照流水线划分模块,代码注释多,便于理解。FPGA验证通过,可综合。
关键技术五级流水线MIPS处理器verilog源码,实现MIPS32的整数指令,代码风格好,注释清晰,适用于计算机体系结构的理解及实践,了解MIPS体系结构有很大帮助
- 2022-04-16 11:12:47下载
- 积分:1
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pps_ketiao_rb2
说明: FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:02下载
- 积分:1
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alu2
verilog alu 8bit for engineers
- 2011-05-26 11:32:21下载
- 积分:1
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信号发生器
一个vivado和matalab混合编程的信号发生器,注意要把vivado里面的核文件路径改一下(A signal generator with mixed programming of vivado and matalab, pay attention to changing the path of the core file in vivado)
- 2019-06-18 10:34:09下载
- 积分:1
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seven-voting
用verilog 语言实现七人投票表决器(verilog seven voting)
- 2020-09-24 10:57:48下载
- 积分:1
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DDR3_256MByte
说明: 基于K7的FPGA的DDR3读写程序,通过串口发送1024位的数据,写到FPGA的DDR3端,然后将数据从DDR3中读取出来,通过串口发送到PC端。(The DDR3 reading and writing program of FPGA based on K7 sends 1024 bit data to DDR3 end of FPGA through serial port, then reads data from DDR3 and sends it to PC through serial port.)
- 2021-02-22 15:19:41下载
- 积分:1
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Kay_algorithm
QPSK调制的载波频偏估计,是一个可以调用的函数。接收端进行了一系列的处理。经典的Kay法(QPSK-carrier frequence offset estimation_ kay )
- 2013-03-18 14:36:29下载
- 积分:1