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FPGA控制AG9226代码
FPGA控制AG9226进行采样的代码,并用signaltap测试了一下其正确性
- 2022-07-21 15:41:56下载
- 积分:1
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dac5686
在FPGA上编写的通过SPI总线配置外部DAC芯片DAC5686的程序,通过板级调试,验证可用。程序通过状态机实现,将需要配置的寄存器值转为SPI总线的数据格式发送出去。 (Configure external DAC chip DAC5686 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀琀漀 SPI bus data format sent.)
- 2014-09-11 11:05:20下载
- 积分:1
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softdemodulation-of-8psk
讲述软解调很不错的一片文档,主要阐述的是8PSK的软解调FPGA实现,但对8PSK的软解调原理阐述很清楚,没有多余的东西,但需要注意其中各个调制符号点得顺序。(About soft demodulation of a document is very good, mainly on the soft 8PSK demodulation FPGA, but soft 8PSK demodulation principle describes very clearly, no extra stuff, but need to pay attention to the point where each modulation symbol was in order.)
- 2014-06-03 14:12:05下载
- 积分:1
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AES128
AES128 encription vhdl code
- 2014-03-05 00:48:13下载
- 积分:1
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有用的VHDL源代码
有用的VHDL源代码-useful VHDL source code
- 2023-08-07 09:00:03下载
- 积分:1
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usetheModelSimtosimulink
说明: 详细介绍了如何使用ModelSim进行仿真.(it will teach you how to use the ModelSim to simulink.)
- 2009-08-05 15:51:29下载
- 积分:1
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verilog.HDL.examples
许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等(many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.)
- 2020-06-26 04:40:02下载
- 积分:1
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用VHDL语言编写一计时范围为59.99秒的跑表
计时范围为59.99秒;有计时开始和停止计时控制,复位控制可以对所有计时进行异步复位;计时结果由四位七段数码管显示。
- 2022-02-13 02:19:25下载
- 积分:1
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Advanced-FPGA-Design
Advanced FPGA Design - Architecture, Implementation, and Optimization(Advanced FPGA Design- Architecture, Implementation, and Optimization)
- 2015-04-13 16:00:33下载
- 积分:1
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可综合的Verilog语法和语义,从大学教师cambri…
《可综合的Verilog语法》国外著名大学老师编写,对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.
- 2022-03-31 07:34:29下载
- 积分:1