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verilog8
Learning Verilog Chinese Version Part 8
- 2012-06-15 06:04:00下载
- 积分：1
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EX7_BINARY2GRAY
本模块是实现格雷码和二进制码的转换，并给出仿真测试文件(This module is to achieve the conversion of Gray code and binary code, and give the simulation test file)
- 2015-04-14 16:48:38下载
- 积分：1
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mul24x24
24位x24位的乘法器
十分详细24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器(24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplication Explorer 24-bit x24 multiplier 24-bit x24-bit multiplier)
- 2009-06-08 10:00:58下载
- 积分：1
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eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
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- 2021-03-07 15:49:29下载
- 积分：1
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参数化 FFT
我在这里附上该程序用于计算数组中的 fft。这里的蝴蝶是首次描述即基本关闭 fft 逻辑。一套是包括包含有可从与复杂的有符号类型转换的功能。Fft_engine 是为实现逻辑的主要程序。
也还会创建用于存储旋转因子在 fpga 上的 vhdl 代码。
- 2022-03-16 05:47:35下载
- 积分：1
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TW2867_ADV7171
FPGA TW2867输入到ADV7171显示实验(FPGA TW2867 input to the ADV7171 display experiment)
- 2021-03-19 15:19:19下载
- 积分：1
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mod3
verilog源代码，实现两种方法的模3运算。(verilog source code，to implement the calculation of mod-3 by two means.)
- 2011-12-24 10:23:40下载
- 积分：1
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suijitu
matlab随即图设计程序，应该比较有用，希望能申请会员成功吧。。(matlab then drawing design program)
- 2013-04-25 10:49:07下载
- 积分：1
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用vhdl来实现的数字频率合成的技术，几乎很全的，所有的都有...
用vhdl来实现的数字频率合成的技术，几乎很全的，所有的都有 -Use VHDL to realize the digital frequency synthesis technology, almost the whole of, all have
- 2022-02-04 17:07:58下载
- 积分：1
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FPGA的I2S接收模块 audio_in_buff
说明： 用于FPGA的I2S接收模块，仅供学习和参考(audio-i2s receive.use fpga.)
- 2019-04-21 12:11:23下载
- 积分：1
