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SinglePeriodCPU
说明： verilog语言书写，单周期CPU源码(single period CPU)
- 2020-11-25 11:59:32下载
- 积分：1
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DDS-Basic-principle
DDS基本原理，详细讲述了DDS基本原理及设计技巧(DDS Basic principle)
- 2015-09-14 21:38:26下载
- 积分：1
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cpldfpga
《CPLDFPGA嵌入式应用开发技术白金手册》源代码，涉及FPGA/CPLD的各个方面，键盘扫描，LED扫描等简单程序及滤波器等的设计(" CPLDFPGA platinum embedded application development technology handbook" source code, related to FPGA/CPLD all aspects of the keyboard scanning, LED scanning filters, such as simple procedures and design)
- 2009-04-20 20:59:16下载
- 积分：1
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SPI_test
说明： 用FPGA于32进行SPI单向通信，FPGA向32放松发送数据(One-way SPI communication is carried out in 32 with FPGA, and data is sent to 32 with ease by FPGA.)
- 2020-06-18 10:40:02下载
- 积分：1
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verilog program for real time clock.. select the .v file to view the code.
verilog program for real time clock.. select the .v file to view the code.
- 2022-01-26 07:14:23下载
- 积分：1
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VHDLgoldbook
VHDL黄金参考手册，能让你更好的学习了解VHDL语言(VHDL gold reference manual, can make you a better learn VHDL language)
- 2013-12-05 16:06:19下载
- 积分：1
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suzimiaobiao
数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)
- 2011-09-20 14:28:30下载
- 积分：1
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TFT_LCD_ASIC_implement
说明： 彩色TFT液晶显示控制电路设计及其ASIC实现(TFT color LCD control circuit design and ASIC realization)
- 2008-10-25 15:11:10下载
- 积分：1
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一个异步FIFO的verilog实现论文
一个异步FIFO的verilog实现论文-err
- 2022-01-28 06:08:18下载
- 积分：1
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vhdl学习方法,含有大量的vhdl源代码,对vhdl的语法的介绍
vhdl学习方法,含有大量的vhdl源代码,对vhdl的语法的介绍-VHDL source习laugh Yang, Yi bleed at the nose cavity submerged stresses measured tungsten Daitou VHDL, VHDL-Qin Pang Yang cavity cavity Geng Zhuang
- 2023-07-17 16:40:03下载
- 积分：1
