-
bianyuanjiance
图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)
- 2020-06-21 13:20:06下载
- 积分:1
-
2
说明: ADV7179芯片的驱动程序,基于FPGA硬件实现,已经验证可以使用(ADV7179 chip drivers, FPGA-based hardware implementation has been verified using)
- 2011-02-21 16:06:56下载
- 积分:1
-
程序是用硬件描述语言(VHDL)实现:4×4键…
程序主要是用硬件描述语言(VHDL)实现:
4*4键盘扫描,简洁明了,通俗易懂,比较适合VHDL初学者-procedure was used in hardware description language (VHDL) to achieve : 4* 4 keyboard scan, concise, easily understood and more suitable for beginners VHDL
- 2022-01-31 18:02:15下载
- 积分:1
-
clock_6
说明: ds1302时钟驱动程序,已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)
- 2020-06-24 12:00:02下载
- 积分:1
-
frequency divider
说明: FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)
- 2019-04-27 23:35:12下载
- 积分:1
-
VHDL语言串口接收数据
VHDL语言,实现穿行数据接收的功能,将异步串口的数据转换为八位数据存储。
- 2022-03-24 16:10:35下载
- 积分:1
-
Detailed description of the FPGA design flow of the entire FPGA design flow full...
详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE
- 2022-11-01 22:10:02下载
- 积分:1
-
ahb_slave_latest.tar
AHB 总线slave verilog实现(Implementation of AHB bus)
- 2020-06-30 13:40:02下载
- 积分:1
-
Manip_NIOS_1
nios processor example 1
- 2015-05-22 00:17:43下载
- 积分:1
-
phase_test
VHDL,简易音频数字相位表的设计与实现 数字相位测量仪在工业领域中经常用到的一般测量工具,主要应用与同频率正弦信号间的相位差的测量显示。
本系统采用FPGA实现测量的核心部分,主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单,整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段,在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理,并将数据传回FPGA进行相位差计数累加、测量运算,最后送显示译码电路显示,测相范围为 ,相位测量误差 < 。
经测试结果验证,本系统充分利用FPGA对数据的高速处理能力,是系统设计高效、可靠,处理速度快,稳定性高,易于实现。
(VHDL, simple audio digital phase Table Design and Implementation of the digital phase meter general measurement tools are often used in the industrial field, the measurement of the phase difference between the main application with the same frequency sinusoidal signal. The system uses the FPGA implementation of the core part of the measurement, mainly by the digital phase, cumulative counter, the decoding circuit of the controller as well as storage and display. The system hardware circuit is simple, and the entire system using hardware description language VHDL system means a description of the internal hardware structure, completed in the XILINX company ISE9.1 software support. The audio signal in the frequency range of 20Hz ~ 20kHz sampling KAM-phase process, and the data returned FPGA retardation counted accumulation measuring operation, and finally sent to the decoding circuit, the scope of the measurement phase, the phase measurement error < . The test results verify the full u)
- 2012-09-24 10:11:57下载
- 积分:1