-
pinlvji
verilog 简易频率计的设置,包括整个工程(verilog simple frequency meter settings, including the entire project)
- 2013-08-18 09:53:52下载
- 积分:1
-
spi
该程序是一个可完成订制化的SPI双向总线接口,时钟相位、极性,以及分频比全部可通过寄存器进行配置,已经在ISE下通过综合,占用资源少,强烈推荐
(The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)
- 2013-07-02 14:07:16下载
- 积分:1
-
3 位到 4 位解码器
此程序将解码 3 位二进制值为自我过渡活动较少的 4 位值。
这是执行 IEEE 文件来解压缩 VLSI 互连线上的数据。
- 2022-06-29 06:38:32下载
- 积分:1
-
RTL_NAND_Flash_controller-master
RTL_NAND_Flash_controller-master,基础入门控制器,内存管理,fpga实现。miicron所属,
- 2022-04-12 05:21:10下载
- 积分:1
-
quartus-mult
mult,在quartusII中,以模块输入形式,仿真乘法器mult,得到时序图和功能图(a simulation example of mult)
- 2012-10-17 14:22:11下载
- 积分:1
-
XAPP134_SDRAM_VHDL
XAPP134 SDRAM VHDL design file
- 2011-01-19 09:57:21下载
- 积分:1
-
cordic
实现可连续输入数据做三角函数变换处理,通过verilog代码实现,(It realizes triangular function transformation for continuous input data.)
- 2020-06-21 22:40:01下载
- 积分:1
-
pwm_smg_display
用三个按键控制pwm输出
key0控制是选着显示/改变频率或占空比
key1控制增加
key2控制减少
数码管显示频率或占空比
频率单位默认Hz(500-20KHz)
占空比范围(0.1-0.9)(Control PWM output with three keys
Key0 controls display/change frequency or duty cycle optionally
Key1 controls the increase
Key2 controls are reduced
Digital tube display frequency or duty ratio
Frequency unit default Hz (500-20khz)
Duty cycle range (0.1-0.9))
- 2020-06-17 15:42:35下载
- 积分:1
-
uart_vivado
说明: UART 收发模块,可移植,编程平台为vivado(uart communication transceiver module, portable)
- 2020-10-17 13:33:10下载
- 积分:1
-
disparity
Disparity mapp code in VHDL
- 2017-11-30 14:48:59下载
- 积分:1