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DE2_PS2_Example
PS2 Module for Altera DE2
- 2017-06-20 21:04:32下载
- 积分：1
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简易信号发生器 FPGA
说明： 简易信号发生器，可以实现简单的信号实现，任意波编辑，通过FPGA的verilog语言实现功能，自测可以正常使用。(Simple signal generator, can realize simple signal realization, arbitrary wave editing, through FPGA Verilog language function, self-test can be used normally.)
- 2021-03-25 11:15:32下载
- 积分：1
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Archive
TASKS OF TWO TYPES CAN BE RUN FOR EVERY 2 MIN.
- 2012-11-14 15:12:43下载
- 积分：1
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用verilog实现UART协议
UART包括发射机和接收机。发送器本质上是一个加载数据的特殊移位寄存器；
- 2022-04-09 00:02:07下载
- 积分：1
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emif2axi_v1_00_a
emif接口转axi接口，在多个项目中使用，功能完善(EMIF interface to Axi interface, used in many projects, perfect function)
- 2020-12-01 15:29:26下载
- 积分：1
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rfid new code
说明： In the data management system a significant role of the Data link layer is to convert the unreliable physical link between reader and tag into a reliable link. Therefore, the RFID system employs the Cyclic Redundancy Check (CRC) as an error detection scheme. In addition for reader to communicate with the multiple tags, an anti-collision technique is required. The technique is to coordinate the communication between the reader and the tags. The common deterministic anti-collision techniques are based on the Tree algorithm such as the Binary Tree and the Query Tree algorithms.
- 2019-04-30 16:54:27下载
- 积分：1
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chaoshengbo_diatance_hc_sr_04
实现Verilog编程，实现超声波测距模块实现测距功能，并将测得的距离显示在数码管上(Verilog programming is realized, ultrasonic ranging module is realized, and the measured distance is displayed on the digital tube)
- 2020-06-17 16:40:02下载
- 积分：1
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DDS_Power
FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。(FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.)
- 2007-04-17 23:43:32下载
- 积分：1
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VHDL语言100例详解
说明： VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。(VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.)
- 2005-09-04 17:15:21下载
- 积分：1
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DA_AD
基于FPGA的AD和DA设计代码及文档(Design code and document of AD and DA based on FPGA)
- 2017-11-07 22:03:30下载
- 积分：1
