verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等(verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other)

VHDL 2FSK调制解调器各部分的原理与代码(The principle and code of each part of the VHDL 2FSK modem)

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。-This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.

本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.

说明：  CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。(CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write registers, read and write memory and execution.)

VHDL实现PI调节的算法。内部使用整数计算，避开了浮点数的运算。仿真结果正确-VHDL realize PI regulator algorithm. Internal use integer calculations to avoid the floating point arithmetic. The simulation results correctly

protel经典教程，并附有一张电路设计原理图(protel classic tutorials, together with a circuit design schematic)

VIVADO 从此开始,详细讲解了vivado,FPGA开发工具的使用，对于初学者学习VIVADO工具很有用。(VIVADO from now on, explained in detail the use of vivado, FPGA development tools, for beginners to learn VIVADO tools very useful.)

TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码(Tail-biting convolutional code encoder verilog code)

包含了VHDL语言的100个例子，如交通灯控制器，空调系统有限状态自动机，FIR滤波器，五阶椭圆滤波器，闹钟系统的控制-VHDL language contains 100 examples, such as traffic light controllers, air-conditioning systems finite state automata, FIR filter, the fifth-order elliptic filter, alarm system control