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设计了一个异步时钟域间进行通行的模块,并采用Modelsim进行仿真验证,仿真结果满足预期的目的。...
设计了一个异步时钟域间进行通行的模块,并采用Modelsim进行仿真验证,仿真结果满足预期的目的。-Designed an asynchronous clock domains between the passage of the module, and use Modelsim for simulation, the simulation results meet the intended purpose.
- 2022-02-04 07:33:00下载
- 积分:1
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VHDL实现ALU的源代码,并且提供了一个详细的testbench!
VHDL实现ALU的源代码,并且提供了一个详细的testbench!-ALU VHDL source code, and provide a detailed testbench!
- 2022-03-12 21:14:39下载
- 积分:1
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ahb 总线协议
本文以 VHDL 语言编码得到了 AMBA 与 AHB 总线仲裁。这里在本文中,我们设计了 AMBA 总线协议,将用于多奴隶通信环境,多主
- 2022-01-25 21:18:17下载
- 积分:1
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shockware
VHDL 波形防止抖动程序,学习试验材料(VHDL prevent jitter waveform procedures, the pilot study materials)
- 2007-03-01 13:15:37下载
- 积分:1
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Verilog--image-sample
基于Verilog的图像采集、处理和存储程序,初学者参考,高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)
- 2021-04-16 11:48:54下载
- 积分:1
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booth4
4位的booth算法加法器,对计算机组成原理的学习有帮助,verilog语言编写(4-bit adder booth algorithm, the learning of computer organization help, verilog language)
- 2010-09-27 04:49:51下载
- 积分:1
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FPGA programming serial communications, the entire source code. Including the si...
FPGA编程实现串口通信,源代码全。包括仿真程序。-FPGA programming serial communications, the entire source code. Including the simulation program.
- 2022-08-25 19:14:53下载
- 积分:1
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xapp953
Two-Dimensional Rank Order Filter
Author: Gabor Szedo
- 2012-05-15 02:50:41下载
- 积分:1
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Case-statement-described-4-1-Mux
用case 语句描述的4 选1 Mux 源码程序,好用(-4 with a case statement described 1 Mux source program, easy to use)
- 2012-10-21 09:47:32下载
- 积分:1
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homework32
说明: 这是32位移位寄存器,是用verilog编写的,能够实现从1到31位的左或右的移位(This is a 32-bit shift register, is prepared verilog, can be realized from the 1-31 shift left or right)
- 2009-07-27 15:54:00下载
- 积分:1