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三角函数的Verilog HDL语言实现
以Actel FPGA作为控制核心,通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波,利用Verilog HDL语言实现死区时间可调的SPWM全数字算法,并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, realize the adjustable dead time using Verilog HDL language of the SPWM digital algorithm and digital SPWM algorithm is realized in Fushion StartKit development board.)
- 2017-07-08 20:59:23下载
- 积分:1
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rams
说明: combinatorial modules
- 2019-04-13 19:41:21下载
- 积分:1
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测试AD9280的功能,用verilog编写
通过verilog编写AD9280的测试程序,将AD9280采集的数据存储到sdram中,然后读取sdram中的数据,发送到串口进行保存。
- 2022-08-12 16:55:30下载
- 积分:1
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lsd
按键控制LED流水灯;按键1按下前8个灯从左到右依次点亮,按键2按下中间前8个灯从左到右依次点亮,按键3按下所有灯全亮(Water control button LED lights sequentially lit buttons the eight lights left to right 1 Press button 2 press from left to right is lit in the middle eight lights, key 3 Press All full bright light)
- 2012-10-17 18:23:36下载
- 积分:1
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dingshi
定时器加数码管显示源码,以及test bench测试模块源码,经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)
- 2013-07-27 10:34:41下载
- 积分:1
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串口通信(发送和接收)
基于verilog语言的串口通信,可以实现数据的发送和接收,代码清晰明了
- 2022-01-21 20:44:37下载
- 积分:1
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MX25L6445E--Verilog--v1.18
MX25L6445E开发时间,Verilog语言(MX25L6445E development time, Verilog language)
- 2011-07-20 15:11:31下载
- 积分:1
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FIFO_UVM_VIP
用uvm验证方法学验证异步fifo,文件包括异步FIFOrtl代码和uvm组件(Verification of asynchronous FIFO with UVM)
- 2021-04-28 09:48:44下载
- 积分:1
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Construction-and-Experimental-Evaluations-of-User
Construction and Experimental Evaluations of User-Centered Power
- 2011-11-29 08:35:34下载
- 积分:1
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Quartus_17.1破解器_Windows_密码12345
quartus 17.1 安装包,我现在用的就是(Quartus 17.1 installation kit, what I am using now is)
- 2018-09-10 20:13:45下载
- 积分:1