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液晶显示器的接口
你好,
- 2023-06-27 06:40:03下载
- 积分:1
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dianzhen
如果需要用verilog设计一项比较简单的功能,那么这个浅显易懂的程序能让你很快明白点阵的设计方法,尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)
- 2014-01-16 16:13:53下载
- 积分:1
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BISS-c协议中英文版本
描述了IC-hus公司推出的BISS-C协议内容,包括单向biss-c协议以及标准biss-c协议(Describes the BISS-C protocol introduced by IC-hus, including the one-way biss-c protocol and the standard biss-c protocol)
- 2021-05-10 10:18:53下载
- 积分:1
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Decoder_CC_P
Convolotional Decoding Based on Viterbi Algorithm
- 2021-05-13 16:30:02下载
- 积分:1
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8832135
一个具有“百分秒,秒,分”计时功能的数字跑表,可以实现一个小时以内的精确至百分之一秒的计时。
数字跑表的显示读者可以通过编写数码管显示程序来实现,本训练只给出数字跑表的实现过程。
读者还可以通过增加小时的计时功能,实现完整的跑表功能。(A " percentage of seconds, seconds, minutes," digital stopwatch timer can be achieved within an hour of precision to the hundredth of a second time. Digital stopwatch readers can display the digital display through the preparation of procedures to achieve, given the training is only the realization of the process of digital stopwatch. Readers can also function to increase hours of time to achieve full stopwatch function.)
- 2009-04-09 13:20:35下载
- 积分:1
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FPGAtraining
远立科技FPGA培训文档,关于GFP项目的一些细节,很好的!(Yuan established FPGA technology training documentation)
- 2011-01-11 13:52:10下载
- 积分:1
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单周期CPU设计完整代码
实验课作业,下载可以直接跑,各个模块的完整代码。
- 2023-09-02 21:10:03下载
- 积分:1
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ff_const_mul
说明: 常系数有限域乘法器,verilog DHL源码(Constant coefficient finite field multiplier, verilog DHL source)
- 2011-02-19 21:09:36下载
- 积分:1
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MifFileGen
VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子,生成的是一个定点的正弦数据表文件,需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)
- 2013-07-19 02:32:45下载
- 积分:1
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FPGA开发程序
针对初学FPGA的人,简单易懂,用notepad++打开可以看到QuartusII里的中文注释,方便学习和开发
- 2022-08-14 07:45:22下载
- 积分:1