-
整个工程代码
掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)
- 2019-01-21 17:21:27下载
- 积分：1
-
A Designers Guide to Asynchronous VLSI
说明： 异步VLSI大规模电路设计的圣经，一本很经典的异步电路入门书籍(The Bible of Asynchronous VLSI Large Scale Circuit Design, A Classic Introduction to Asynchronous Circuits)
- 2020-06-23 21:40:02下载
- 积分：1
-
ADPCM
说明： APPCM算法和AD/DA芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境(APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment)
- 2009-08-22 10:07:03下载
- 积分：1
-
gtx_aurora_zc706_clock_module
对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)
- 2018-01-23 09:03:31下载
- 积分：1
-
Amp-diagrams_pack
Diagram and how-to-make instructions pack of 6 diferent Amplifiers
- 2010-10-24 18:40:43下载
- 积分：1
-
2581
Complex of three-point Gauss-lengend the Formula pi, Including orbital maneuvering simulation, initial orbit calculation, University of numerical analysis algorithms.
- 2017-09-03 10:42:39下载
- 积分：1
-
FPGA
无线通信FPGA实现的代码 有matlab和verilog(FPGA implementation of wireless communication code matlab and verilog)
- 2012-09-17 10:39:40下载
- 积分：1
-
VHDL
控制电话信令
完成忙碌 等待 回铃音振铃等(Signaling complete control over telephone ring so busy waiting ringback tone)
- 2010-10-22 20:11:38下载
- 积分：1
-
并行LMS均衡FPGA实现
实现FPGA的并行LMS均衡，主要是均衡计算权值系数的算法过程，verilog语言，模块的输入为输入的X信号，输出为权值系数W，以及最后的输出Y。实现了LMS 的并行均衡过程
- 2023-09-08 06:15:03下载
- 积分：1
-
i2c的systemverilog vip，功能齐备，架构简洁
i2c的systemverilog vip，功能齐备，架构简洁她是用SystemVerilog写的验证模型，支持master和slave模式，支持stop bit和start bit的产生
- 2022-07-06 10:34:50下载
- 积分：1
