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                        facman
                        
                          一款在Verilog实现的吃豆人游戏,采用VGA接口,在Nexys3开发板上运行无误。(A pac-man game implemented via Verilog, using VGA interface, perfectly run on Nexys 3)                         
                            - 2021-03-31 07:39:09下载
- 积分:1
 
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                        ad9740控制程序
                        
                          FPGA控制DA(AD9740)的程序代码,包含mif文件,基于verilog编写,已调试通过。                         
                            - 2022-03-22 16:12:00下载
- 积分:1
 
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                        automachine
                        
                          自动售货机的状态机实现
自动售货机的状态机实现(this is a automachine)                         
                            - 2011-07-06 13:40:28下载
- 积分:1
 
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                        LMS算法FPGA仿真
                        
                          自适应滤波器算法LMS ,的FPGA实现,采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)                         
                            - 2020-06-24 01:00:02下载
- 积分:1
 
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                        UART的FPGA代码
                        
                          串口代码,FPGA实现,可以直接给出结果,可以仿真并实现                         
                            - 2022-03-14 11:01:41下载
- 积分:1
 
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                        SDRAM
                        
                          说明:  SDRAM的驱动程序,主要是对SDRAM各类状态进行驱动,有刷新模块、读、写模块等。(The driver of SDRAM mainly drives various states of SDRAM, including refresh module, read and write module.)                         
                            - 2020-06-23 01:40:02下载
- 积分:1
 
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                        PulseWidth_detector_VHDL
                        
                          通信控制中常用的脉冲宽度检测程序,VHDL模块化编成实现(原创)(communication control used in pulse width detection procedures, VHDL modular organization to achieve (original))                         
                            - 2007-03-28 17:41:46下载
- 积分:1
 
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                        IEEE_030_powerworld
                        
                          The IEEE 30-bus modified test system has 6 synchronous machines with IEEE type-1 exciters, 4 of which are synchronous compensators, 36 buses, 37 transmission lines, 10 transformers and 21 constant impedance loads. The total load demand is 283.4 MW and 126.2 MVAr.                         
                            - 2020-07-03 02:20:02下载
- 积分:1
 
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                        Xilinx 7系列FPGA资料
                        
                          说明:  对fpga的学习有一点帮助,属于较为基础的部分(It has a little help to the study of FPGA, which belongs to the more basic part)                         
                            - 2021-04-07 12:03:10下载
- 积分:1
 
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                        AHBtoAPB
                        
                          说明:  amba总线桥:ahb to asb!verilog hdl文档加代码,非常全,soc(amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc)                         
                            - 2021-01-05 03:48:55下载
- 积分:1