-
Snacke
基于NiosII系统的可以在DE2-115板子上运行的吞食蛇游戏！（可以使用RS2键盘进行控制）(DE2-115 board NiosII system swallowed snake game! , (RS2 keyboard control))
- 2013-01-01 10:12:03下载
- 积分：1
-
一种用于乘数的8x8的制备采用Verilog HDL语言
一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
- 2023-08-11 06:05:03下载
- 积分：1
-
LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现
LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language
- 2022-12-16 00:40:03下载
- 积分：1
-
利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块...
利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed source code as well as the design process, the module
- 2022-02-25 00:52:03下载
- 积分：1
-
等精度测频??
等精度测频法，有需要的可以下载看看哟，word中包含的代码(Equal Precision Frequency Measurement Method)
- 2020-06-22 11:00:01下载
- 积分：1
-
十六进制7Segment时钟
十六进制计数器递增 ALTERA FPGA 板 7 段显示器上的每一秒。
- 2022-07-13 21:46:37下载
- 积分：1
-
VHDL_biss
FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)
- 2021-03-15 19:19:22下载
- 积分：1
-
Detailed description of the FPGA design flow of the entire FPGA design flow full...
详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE
- 2022-11-01 22:10:02下载
- 积分：1
-
qpsk_mod_demod
qpsk调制解调，结果可以通过示波器进行观察(qpsk modulation and demodulation, the results can be observed by an oscilloscope)
- 2015-03-19 12:25:02下载
- 积分：1
-
ytupn
Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.
- 2017-09-02 18:07:13下载
- 积分：1
