-
一个有关于UART开发的自己的一个VHDL代码
一个有关于UART开发的自己的一个VHDL代码-A UART has developed its own about a VHDL code
- 2023-03-01 05:35:04下载
- 积分:1
-
design through verilog hdl
design through verilog hdl
- 2023-04-07 06:25:04下载
- 积分:1
-
全部通过,是我的精心设计,完全满足初学者的要求。
全部通过,是我的精心设计,完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
- 2022-03-02 01:44:58下载
- 积分:1
-
avoidance-radar
汽车在防撞雷达方向的研究的详细原理的介绍(Introduction of detailed schematic of the car in the direction of the anti-collision radar)
- 2013-01-06 14:01:47下载
- 积分:1
-
a program which divides the clock by 3
a program which divides the clock by 3
- 2022-01-25 14:21:33下载
- 积分:1
-
agc
数字自动增益控制 AGC (automatic gain control) Verilog(automatic gain control Verilog)
- 2021-03-11 19:29:25下载
- 积分:1
-
fpga数码管显示
让你EJ疼没人开门吗维护和输入热火男的竟然也可以看看一份心疼你身边女人很多好的主人你让他愤怒和难题太难太难太难输入你的人难道她和他人的烦恼的童年听到她赫然发红包少年人反而能认识的男人的法人俄方的人体内
- 2023-01-03 09:40:17下载
- 积分:1
-
SRAM
进阶实验之SRAM测试,由verilog编写,可直接对sram进行存写(Advanced SRAM test experiments, written by the verilog, can be stored directly on the sram write)
- 2011-08-18 01:58:56下载
- 积分:1
-
真正成为一个母版页,然后必须了解和使用DHTML。这里省…
成为真正的网页制作的高手的话,必须了解并使用DHTML.这里提供了最好的手册和文档.-become truly a master pages, then have to understand and use DHTML. Here to provide the best manuals and documents.
- 2023-03-13 00:40:03下载
- 积分:1
-
primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used stora...
本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件,完全的代码在ALTERA的FPGA上已经通过仿真测试,保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
- 2022-07-07 05:54:22下载
- 积分:1