登录
首页 » VHDL » 08EE06EDA 实验 4(VHDL 状态机设计_序列检测器)6/7/2008

08EE06EDA 实验 4(VHDL 状态机设计_序列检测器)6/7/2008

于 2022-03-29 发布 文件大小:22.25 kB
0 46
下载积分: 2 下载次数: 1

代码说明:

08EE06EDA 实验 4(VHDL 状态机设计_序列检测器)6/7/2008-design thesis requirement by vhdl

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 一篇比较好的spi接口的vhdl实现的参考
    一篇比较好的spi接口的vhdl实现的参考-A relatively good spi interface realize VHDL reference
    2023-05-08 20:50:03下载
    积分:1
  • encoder_Z64_all_rate
    Wimax矩阵的LDPC编码器,已通过modelsim仿真测试,并前在altera的FPGA板上通过测试,码率5/6,可进入代码内部修改参数,支持2/3,3/4其他2个码率,数据吞吐量为700M(Wimax based LDPC encoder, modelsim simulation passed, also passed on altera FPGA board, code rate 5/6, also support 2/3,3/4, throughout 700m)
    2012-03-19 09:44:32下载
    积分:1
  • Muliplexer
    说明:  Multiplexer 4 to 1 on Modelsim
    2020-10-14 13:56:09下载
    积分:1
  • multifre
    说明:  资料的内容是实现旋转机械同步整周期采样的数据采集系统相关文献资料,包括鉴相信号如何倍频,机械振动信号相位如何检测等的实现方法。(Information content is for rotating mechanical synchronization synchronous sampling data acquisition system-related documents, including the Kam-believe number to harmonic mechanical vibration signal phase to detection of realization.)
    2010-04-26 15:56:20下载
    积分:1
  • ISE7.1,采用VIRTEX
    ISE7.1,采用VIRTEX-II芯片。实现adc数据采样,平均,通道选择,采样时钟选择,数据格式调整,内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
    2022-03-28 19:34:46下载
    积分:1
  • vhdl
    vhdl表示与综合,原书第二版,中文版,比较全,用超星打开-vhdl
    2023-05-18 10:30:04下载
    积分:1
  • apb.v
    AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
    2021-04-17 20:38:53下载
    积分:1
  • practical_lift_controller 实用电梯控制器 实用电梯控制系统block symbol file 实用电梯控制器的Verilo
    practical_lift_controller 实用电梯控制器 实用电梯控制系统block symbol file 实用电梯控制器的Verilog HDL程设计-practical utility practical_lift_controller elevator controller elevator control system block symbol file utility elevator controller Verilog HDL-way design
    2023-03-27 22:00:04下载
    积分:1
  • MP3-coder
    In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them includes all the VHDL source codes of the component.)
    2013-08-06 15:40:24下载
    积分:1
  • lowpass
    低通滤波器(由matlab和simulink两种方法实现)源文件及图片示例(Low-pass filter) source file and photo examples (by the two methods matlab and simulink)
    2013-03-13 18:36:40下载
    积分:1
  • 696524资源总数
  • 103938会员总数
  • 55今日下载