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shuzishizhong
基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能(DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time)
- 2020-11-01 11:39:54下载
- 积分：1
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23
说明： 基于FPGA的液晶显示控制器的设计，FPGA用的是EP2C5,LCD用的是ST7920内核的122*32点阵的LCD，显示中西文字符(FPGA-based LCD display controller design, FPGA is used EP2C5, LCD is used in the ST7920 core of 122* 32 dot matrix LCD, display of Chinese and Western characters)
- 2009-06-19 22:01:23下载
- 积分：1
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ahdl--sine-wave-code-with-rom-look-up-table_imp
hi this is an verilog codes
- 2011-11-11 14:30:21下载
- 积分：1
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05_fifo_test
说明： FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
- 2021-04-08 22:19:20下载
- 积分：1
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用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看...
用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
- 2022-09-01 11:30:03下载
- 积分：1
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FPGA-basedhardwareimplementationofneuralnetworks
基于FPGA的神经网络硬件实现中的关键问题研究，适合用fpga研究神经网络的工程人员参考(FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works)
- 2009-04-15 05:44:09下载
- 积分：1
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一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形...
一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形-An accurate clock source to the 0.01s for the beginner to understand VHDL helpful not only to the simulation waveform of the source
- 2022-02-19 22:00:27下载
- 积分：1
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fpga DDS ROM数据正弦波形正半周采样程序
fpga DDS ROM数据正弦波形正半周采样程序-fpga DDS ROM sinusoidal waveform is a half weeks of data sampling procedures
- 2022-03-09 21:09:04下载
- 积分：1
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hex_counter-2014-10-15
hex_counter
old project, please let me know if need any help
- 2014-12-03 02:21:05下载
- 积分：1
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MAX531串行DA芯片的VHDL驱动，我应经在实际工程中试验过！
MAX531串行DA芯片的VHDL驱动，我应经在实际工程中试验过！-MAX531 serial DA chip VHDL driver, I shall be in the actual project tested!
- 2022-02-05 14:43:19下载
- 积分：1
