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clock-generation
长帧同步时钟的产生， 源码程序，实验好用(Long frame synchronization clock generation, source program, easy to use experimental)
- 2012-10-21 09:52:08下载
- 积分：1
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AD9226
一个AD9226芯片的驱动，用FPGA写的。虽然简单，但是希望对各位有帮助(An AD9226 chip driver, FPGA written. Though simple, but I hope you will help)
- 2013-09-05 01:47:36下载
- 积分：1
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- 2022-06-02 03:55:25下载
- 积分：1
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VerilogFreq-div
Verilog分频程序原理讲解及代码.偶数倍分频奇数倍分频的原理和方法(Verilog divide the program explain the principle and code an even multiple of odd multiple of the principle of divide and divide)
- 2013-01-21 21:45:08下载
- 积分：1
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利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块...
利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed source code as well as the design process, the module
- 2022-02-25 00:52:03下载
- 积分：1
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RISC(精简指令集计算机)存储程序状态机的源代码
RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine
- 2022-06-30 22:23:03下载
- 积分：1
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北大verilog课件，数字集成电路设计入门，从HDL到版图
北大verilog课件，数字集成电路设计入门，从HDL到版图-North Verilog courseware, digital IC design entry, from HDL to the map
- 2022-07-24 16:14:44下载
- 积分：1
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VGA altera detailed description of the official routine Verilog code for a very...
详细介绍了VGA官方例程Verilog代码，非常好很实用
- 2022-08-21 17:43:09下载
- 积分：1
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fir
该程序实现了一个FIR滤波加速器，该程序在FPGA板上开发，通过使用VHDL语言来定义RS232端口的使用(design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language. )
- 2013-06-07 06:27:32下载
- 积分：1
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VHDL的应用：USB
VHDL的应用：USB-BLASTER的原理图-VHDL FOR USB-BLASTER
- 2022-04-23 08:50:27下载
- 积分：1
