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fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过...
fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
- 2023-07-19 00:45:03下载
- 积分：1
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32_lvds_test
Xilinx 公司Spartan-6系列FPGA实现LVDS，带Modelsim仿真文件，已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)
- 2020-11-30 20:59:27下载
- 积分：1
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AD9226
FPGA控制AG9226进行采样的代码,并用signaltap测试了一下其正确性(FPGA control AG9226 to sample the code, and use signaltap to test the correctness of the demo.)
- 2020-12-19 17:19:09下载
- 积分：1
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WORK
运用VC编程的带LCD显示的信号发生器可用三个开个调节输出三个波形(Signal generator can be used three to open a regulator output waveform using VC programming with LCD display)
- 2013-03-02 16:13:27下载
- 积分：1
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用FPGA 是先键盘的程序，is good for you
用FPGA 是先键盘的程序，is good for you -FPGA is the first keyboard to use the procedure, is good for you
- 2023-08-22 22:30:03下载
- 积分：1
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sram_060803
SRAM的读写代码，对SRAM进行了乒乓操作，用VHDL语言进行设计，很有参考价值，甚至可以直接复制代码来进行自己的设计(SRAM read and write code, ping-pong operation carried out on the SRAM, using VHDL language design, of great reference value, or even directly copy the code to carry out their own designs)
- 2020-12-04 10:39:24下载
- 积分：1
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UART
本代码用verilog语言配合sopc和nios实现了串口调试的目的。软件编程用C语言描述，只是比较简单的例子，适合初学者做了解用，本人亲自在EP2C8Q上实践。(The code to use verilog language sopc and nios achieved with serial debugging purposes. Software programming using C language description, but relatively simple example for beginners to do with understanding, I personally EP2C8Q on practice.)
- 2013-09-11 10:48:17下载
- 积分：1
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fft
运用matlab实现fft变换，用于地震资料频谱分析！(FFT transform)
- 2013-09-01 16:41:57下载
- 积分：1
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Quartus II TimeQuest时序分析器说明书
说明： Quartus II TimeQuest 时序分析器说明书；这本手册包含一组设计场景、约束指南以及相关建议。您应该熟悉 TimeQuest Timing Analyzer 和 Synopsys Design Constraint(SDC) 的基础知识，以便正确地使用这些指南。(Quartus II timequest timing analyzer manual; this manual contains a set of design scenarios, constraint guidelines, and related recommendations. You should be familiar with the basics of timequest timing analyzer and Synopsys design constraint (SDC) to use these guidelines correctly.)
- 2020-08-07 17:48:31下载
- 积分：1
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FPGA开发全攻略
FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)
- 2017-12-12 16:30:52下载
- 积分：1
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