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基于Verilog HDL的完整数字跑表工程,在试验机台上运行验证通过了的。
用8位7段数码管分别显示微妙,秒,分。
有开始,暂停,复位功能。
学习...
基于Verilog HDL的完整数字跑表工程,在试验机台上运行验证通过了的。
用8位7段数码管分别显示微妙,秒,分。
有开始,暂停,复位功能。
学习VerilogHDL的经典例子,添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.
- 2022-12-27 19:50:04下载
- 积分:1
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一个简单的微处理器的实现,能够进行几种常见的操作,对于熟悉计算机的工作原理很有帮助,并且附有详细的设计报告和设计思路。在word文档最后给出了源代码。...
一个简单的微处理器的实现,能够进行几种常见的操作,对于熟悉计算机的工作原理很有帮助,并且附有详细的设计报告和设计思路。在word文档最后给出了源代码。-a simple microprocessor to achieve, for several common to the operation of the computer for those familiar with the working principle helpful, and with the detailed design reports and design ideas. The word is the final document source code.
- 2022-10-31 15:10:02下载
- 积分:1
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deng
HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示(HDL Verilog electronic code lock input errors have prompted alarm input is correct)
- 2012-06-27 19:25:53下载
- 积分:1
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farrow
该程序实现多项式分数延迟(farrow)的设计。(The program polynomial fractional delay (farrow) design.)
- 2014-12-11 10:21:39下载
- 积分:1
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用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。...
用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-02-25 16:18:57下载
- 积分:1
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Verilog-design-and-identify-book
找到这本书的完整版了。呵呵,贴出来和大家共享。这是本好书,我买了一本作为Verilog的参考书。这本书语法部分集中,便于查阅,此外讲了很多实用的设计思想。最重要的是本书薄,可以完整看完。强烈推荐。
(如果只是查阅,电子版就可以,如要完整学习,建议还是买纸质版的)(Find the full version of this book. I posted and share. This is a good book, I bought a reference book as Verilog. Syntax in this book section focuses on ease of reference, in addition to speaking a lot of useful design ideas. The most important thing is that the book is thin, you can complete reading. Highly recommended. (If you only access the electronic version to complete learning, suggestions or to buy the paper version))
- 2012-06-07 21:58:19下载
- 积分:1
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8位CPU的VHDL设计代码没有测试
8 bit cpu vhdl design code not tested
- 2022-03-21 20:07:37下载
- 积分:1
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EX7_BINARY2GRAY
本模块是实现格雷码和二进制码的转换,并给出仿真测试文件(This module is to achieve the conversion of Gray code and binary code, and give the simulation test file)
- 2015-04-14 16:48:38下载
- 积分:1
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VGA字符显示VHDL程序
可以直接用于工程的设计与开发
VGA字符显示VHDL程序
可以直接用于工程的设计与开发-VGA display characters can be directly used for VHDL design and development
- 2022-01-24 18:21:47下载
- 积分:1
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verilog to write a telephone billing program
verilog 写的 电话计费器程序-verilog to write a telephone billing program
- 2023-01-29 16:55:03下载
- 积分:1