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VHDL digital system design and engineering practice, one that contains principle...
VHDL数字系统设计和工程实践2，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.
- 2022-02-11 12:04:45下载
- 积分：1
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mdct_latest.tar
mdct, it contains DOC,MATLAB,source,synthesis.
- 2009-12-11 14:15:39下载
- 积分：1
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uart(可综合)
说明： 【实例简介】用Verilog实现uart串口协议，波特率可选9600、19200、38400、115200。8位数据为，1位校验位，1位停止位。
【实例截图】
【核心代码】核心代码包括TX，RX，Baud，FIFO([example introduction] UART serial port protocol is implemented with Verilog, and the baud rate can be 9600, 19200, 38400, 115200. 8-bit data, 1 bit check bit, 1 stop bit.
[example screenshot]
[core code] the core code includes TX, Rx, baud and FIFO)
- 2020-12-08 16:00:16下载
- 积分：1
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qts_qii55002
ALTERA on chip fifo. this document is from altera. good resouce
- 2010-09-26 22:12:17下载
- 积分：1
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wbm
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.(algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.)
- 2006-07-12 14:49:35下载
- 积分：1
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3。这个核心的分配必须是免费的。充电
3. Distribution of this core must be free of charge. Charging is -- allowed only for value added services. Value added services -- would include copying fees, modifications, customizations, and -- inclusion in other products.-3. Distribution of this core must be free of charge. Charging is-- allowed only for value added services. Value added services-- would include copying fees, modifications, customizations, and-- inclusion in other products.
- 2022-01-31 13:42:46下载
- 积分：1
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8051参考设计，和其他免费知识产权在8051相比，相对整个D。
8051参考设计，与其他8051的免费IP相比，文档相对较全，Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
- 2023-01-19 15:30:04下载
- 积分：1
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出租车的计费系统，通过这个文件可以清楚地了解出租车的计费原理。...
出租车的计费系统，通过这个文件可以清楚地了解出租车的计费原理。-Taxi billing system, the adoption of the document can be a clear understanding of the accounting principle of a taxi.
- 2022-02-04 05:01:32下载
- 积分：1
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3Digit_7segment_ind_decoder
3 Digit BCD to 7 segment indicator decoder
- 2015-03-05 16:49:04下载
- 积分：1
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QPSK_demod
说明： QPSK的解调程序，采用Verilog编写而成(QPSK demodulation program, written by Verilog)
- 2020-02-29 19:51:38下载
- 积分：1
