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有关verilog的硬件实现VGA设计的代码。
有关verilog的硬件实现VGA设计的代码。-On the Verilog hardware design realize VGA code.
- 2022-07-17 09:16:28下载
- 积分：1
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RAM
这是个双端口双端口ram的定义，当然读者在此基础上还可以扩充(This is a dual-port dual-port ram definition, of course, on the basis of the readers can also be expanded)
- 2009-05-24 11:41:19下载
- 积分：1
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FPGASPI
FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)
- 2020-12-09 13:49:20下载
- 积分：1
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DC-DC
/功 能：1.实现与CPLD的通信,从而控制PWM的占空比. 2.实现LCD显示相关信息.
// 3.实现对键盘按键的判断和确定相应的操作. 4.实现对电压电流的检测.
// 5.实现过载保护功能,电流过大时,切断PWM输出,当排除过流故障后,自动恢复供电
// 6.实现用PID算法跟踪电压,实现稳压输出(/ Function: 1. Achieve communication with the CPLD to control the PWM duty cycle. 2 LCD Display relevant information.// 3. Realize the keyboard keys judgment and determine the appropriate action. 4. Achieve the voltage and current Detection// 5. achieve overload protection, current is too large, cut off the PWM output, when excluding overcurrent fault, automatically restore power// 6. achieve tracking voltage with PID algorithm to achieve the regulated output)
- 2013-05-23 16:28:30下载
- 积分：1
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A NiosII available LCD12864 IPcore, with examples
一个NiosII可用的LCD12864 IPcore，含例子-A NiosII available LCD12864 IPcore, with examples
- 2022-03-23 15:10:17下载
- 积分：1
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HART-HT2015
HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)
- 2013-07-16 17:23:16下载
- 积分：1
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Waveform-generation-program
基于VHDL语言的波形发生器编程设计，能够实现常用波形的产生。(Waveform generator design based on VHDL programming, to achieve common waveform generated.)
- 2014-05-05 16:50:23下载
- 积分：1
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FPGA控制AD7321的模块
FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档(Fpga control module of ad 7321, is I personally tested. Verilog source code, and simple documentation)
- 2018-01-31 20:04:27下载
- 积分：1
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Sequence Detection VHDL source code, ATERA platform compile. Report detailed des...
序列检测VHDL源代码，ATERA平台编译。详细的报表说明和模拟源代码。
- 2022-10-18 04:30:03下载
- 积分：1
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240188modified-rom-based-logic
Modified rom based logic
- 2016-04-01 09:48:45下载
- 积分：1
