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一个基于Verilog语言的简单处理器

于 2022-04-10 发布 文件大小:941.37 kB
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代码说明:

     该程序为使用Verilog HDL语言设计的一个可以根据输入的指令完成不同的操作的简单处理器,可实现mv,mvi,add,sub四个汇编指令,并且使用Quartus II可对该程序进行仿真,最后下载至DE2开发板中可对处理器功能进行验证。

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