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half_adrrrrder
FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)
- 2013-12-01 12:01:31下载
- 积分：1
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本设计是针对LEON3 Altera Nios II startix2
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the
- 2022-05-18 19:00:04下载
- 积分：1
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7941952NCO_sin
NCO 代码设计 使用VHDL语言 (nco)
- 2009-05-23 16:39:37下载
- 积分：1
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雷达 相参积累
给出了脉冲多普勒雷达相参积累的vhdl程序，可作为参考。主要的是设计思想，看之前得掌握相参积累的原理
- 2022-04-25 09:45:07下载
- 积分：1
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CH4CH2CH1VHDL 数字电路参考书所有程序8
CH4CH2CH1VHDL 数字电路参考书所有程序8-CH4CH2CH1VHDL digital circuit reference all proceedings 8
- 2022-08-15 03:26:04下载
- 积分：1
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verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的...
verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the
- 2023-03-24 01:00:04下载
- 积分：1
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AVR IP CORE
可以直接用于工程的开发和
已经通过编译和仿真
AVR IP CORE
可以直接用于工程的开发和
已经通过编译和仿真-AVR IP CORE can be directly used for project development and has passed the compiler and simulation
- 2022-02-15 18:01:54下载
- 积分：1
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20181060261-李康_3
说明： 秒表的实现，有暂停清零功能，Quartus II(Stopwatch realization, has the pause clear function)
- 2020-12-26 15:56:03下载
- 积分：1
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concurrent
VHDL operators basics
- 2013-09-10 14:44:51下载
- 积分：1
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一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧...
一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly
- 2022-01-26 05:10:10下载
- 积分：1
