登录
首页 » VHDL » making a simple clock using altera vhdl

making a simple clock using altera vhdl

于 2022-04-16 发布 文件大小:1.62 kB
0 172
下载积分: 2 下载次数: 1

代码说明:

making a simple clock using altera vhdl

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • lmf
    在ISE下,FPGA产生线性调频信号,并且产生信号的参数可调(In ISE, the FPGA generates a linear frequency modulation signal, and the parameters of the signal are adjustable.)
    2018-03-29 15:31:15下载
    积分:1
  • bt656_decode
    将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
    2021-01-28 10:38:35下载
    积分:1
  • SineGen
    Basic VHDL code to create a sine wave generator for an FPGA board.
    2014-01-24 01:04:15下载
    积分:1
  • wallace_multiplier
    华莱士树乘法器,运用了华莱士树状结构和布斯算法,提高了速度(The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed)
    2020-12-26 10:29:03下载
    积分:1
  • Quartus senior io distribution, manual example
    quartus 中,高级io分配,手动的例子-Quartus senior io distribution, manual example
    2022-07-11 02:00:46下载
    积分:1
  • Xilinx vivado authoritative course
    Xilinx vivado 权威教程,清华大学出版社出版,何宾编著。(Xilinx vivado authoritative course, published by Tsinghua University Press, edited by He Bin.)
    2019-02-19 20:37:09下载
    积分:1
  • uart_byte_rx
    libero soc工程,实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)
    2020-06-21 09:20:01下载
    积分:1
  • 本项目是基于SR和D触发器的使用vhdl.this是100正确的内容。
    this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
    2022-06-27 01:31:46下载
    积分:1
  • Traffic_RYG
    说明:  交通灯的控制,分主干道和从路交通灯,主路优先,正常情况下,绿灯60s,红灯30S,黄灯5S(Traffic light control)
    2020-06-21 06:40:02下载
    积分:1
  • PmodHMT
    Demo 使用 PmodHMT 模块实时检测环境温度和湿度。(The Demo uses PmodHMT modules to detect environmental temperature and humidity in real time.)
    2017-07-30 15:39:55下载
    积分:1
  • 696516资源总数
  • 106783会员总数
  • 25今日下载