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verilog_DATA_displays
使用verilog语言,滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)
- 2014-01-16 10:49:55下载
- 积分:1
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基于任意波形发生器的实现可编程逻辑器件…
基于可编程逻辑器件实现任意波形发生器VHDL源代码-Programmable logic device based on the arbitrary waveform generator implementation VHDL source code
- 2023-05-09 22:45:03下载
- 积分:1
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SV-Combinational-Logic
system Verilog combinational logic
- 2017-01-24 18:50:29下载
- 积分:1
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介绍了FPGA设计的十大准则,对初学者很有用,对于工作多年的同志,也会有整理总结的好处...
介绍了FPGA设计的十大准则,对初学者很有用,对于工作多年的同志,也会有整理总结的好处-Describes the FPGA design of the top ten criteria are useful for beginners, for many years comrades, there will be finishing the benefits of the summary
- 2022-05-09 01:58:50下载
- 积分:1
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华为 Verilog基本电路设计指导书
说明: 华为 Verilog基本电路设计指导书--本文列举了大量的基本电路的Verilog HDL 代码,使初学者能够迅速熟悉基本的HDL 建模;同时也列举了一些常用电路的代码(Huawei Verilog basic circuit design instruction)
- 2020-07-04 11:00:01下载
- 积分:1
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digital scan conversion modules, the digital content can scan, which can also be...
数码扫描显示转换模块,可以对数码内容进行扫描,同时可进行转换-digital scan conversion modules, the digital content can scan, which can also be converted
- 2022-06-14 06:36:33下载
- 积分:1
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eetop.cn_dds
基于verilog的DDS设计,内附代码,仿真环境等说明(the DDS design based on verilog)
- 2015-07-14 08:20:51下载
- 积分:1
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verilog
VERILOG设计实例,非常详细的例子,有交通灯,频率计,数字跑表等等例子(Verilog design example, a very detailed examples have traffic lights, frequency meter, digital stopwatch, etc. Examples of)
- 2008-05-28 22:12:57下载
- 积分:1
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非常好的VHDL音乐
library ieee;
use
ieee.std_logic_1164.all;
use
ieee.std_logic_unsigned.all;
entity song is
port(clk_4MHz,clk_4Hz:in std_logic;
----预置计数器和乐谱产生器的时钟
digit:buffer std_logic_vector(6 downto 0); ----高、中、低音数码管指示
zero:out std_logic_vector(4 downto 0); ----用于数码管高位置低
- 2022-12-29 04:50:03下载
- 积分:1
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verilog 我自己写得按单脉冲发生器,通过了综合和仿真,和频率可变的正弦波发生器,...
verilog 我自己写得按单脉冲发生器,通过了综合和仿真,和频率可变的正弦波发生器,-verilog I write by a single pulse generator, through the synthesis and simulation, and variable frequency sine wave generator,
- 2022-04-19 00:17:00下载
- 积分:1