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(2,1,9)卷积编解码器,译码部分采用Vitebi译码算法,设计使用Verilog HDL语言,在Modelsim平台下仿真通过
(2,1,9)卷积编解码器,译码部分采用Vitebi译码算法,设计使用Verilog HDL语言,在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through
- 2022-05-25 02:39:25下载
- 积分:1
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这些是Verilog文件但我上传文本格式(记事本)
these are verilog files but i am uploading in text(notepad) format
- 2022-12-19 09:00:04下载
- 积分:1
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LCD的Spartan3E FPGA VI
LCD SpartaN3E fpga vi
- 2022-01-29 03:37:34下载
- 积分:1
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jitter_eliminate
verilog描述的实用消抖电路,采用三个D触发器和一个JK触发器。使用emacs编写源文件,iverilog仿真通过,内有png仿真图像截屏(verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots)
- 2009-11-24 15:51:44下载
- 积分:1
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高速FIFO,verilog设计。速度高达130Mhz
高速FIFO,verilog设计。速度高达130Mhz-High-speed FIFO, verilog design. Speed up to 130MHz
- 2023-06-26 05:15:03下载
- 积分:1
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CIC
Efficient CIC filter Implementation using VHDL
- 2010-11-19 08:54:23下载
- 积分:1
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verilog实现的“状态机实现AD574数模转换”
verilog实现的“状态机实现AD574数模转换”-verilog to achieve a " state machine to achieve AD574 digital-analog conversion"
- 2023-01-02 18:45:07下载
- 积分:1
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encode
(7 4)汉明编码源程序,简单实用,可供大家下载,如有问题,望大家多多包含!((74) Hamming code source, simple and practical, available for everyone to download and, if problems, hope you lot included!)
- 2010-01-13 11:37:25下载
- 积分:1
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scope_VGA
利用IIC接口的4路 ADC max1037,采集思路信号,通过在FPGA内部的构建DeltaSigma DAC软核,在VGA液晶显示屏上显示波形。 (IIC interface 4-way ADC max1037, collecting ideas signal the FPGA internal build DeltaSigma DAC soft-core VGA LCD display waveforms.)
- 2012-07-24 00:41:29下载
- 积分:1
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FIR滤波器的VHDL语言实现
FIR滤波器的VHDL语言实现-The implement of FIR Filter based on VHDL
- 2022-01-24 13:17:20下载
- 积分:1