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JESD204B_character
JESD204协议简单透彻的讲解,对做高速AD的朋友有一定的帮助(Understanding control characters in JESD204)
- 2014-10-11 16:17:23下载
- 积分:1
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XilinxISE9.2andChinpScopePro9.2Sn
Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn
- 2021-03-29 15:29:11下载
- 积分:1
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Ldpc_DecodeV1
block-LDPC 译码VHDL 源代码(block-LDPC decode VHDL source)
- 2011-09-13 11:28:53下载
- 积分:1
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SPI_test
说明: 用FPGA于32进行SPI单向通信,FPGA向32放松发送数据(One-way SPI communication is carried out in 32 with FPGA, and data is sent to 32 with ease by FPGA.)
- 2020-06-18 10:40:02下载
- 积分:1
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Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP...
Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)
- 2022-02-12 19:56:59下载
- 积分:1
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多功能信号发生器
采用quartusⅡ仿真软件实现多功能信号发生器的FPGA设计,当输入端有时钟信号输入时,各个信号发生器模块独立运行,独立存在,发出各种信号,这些信号作为数据选择器的输入信号,在数据选择器的作用下,波形切换到相应的模块输出,将通过示波器显示出相应的波形图。
- 2023-04-09 20:10:34下载
- 积分:1
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fpalign_struct
floating point alignment
- 2013-03-11 16:53:31下载
- 积分:1
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VHDL出租车计费代码
该代码实现出租车计费功能,例如起步价为5元,按住相关控件后,每隔五秒,计数将加1,实现类似于开车时计费的功能,当松开按键后,计费也将停止。。。。
- 2022-02-14 00:52:30下载
- 积分:1
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蓝牙HCI―UART与并口的FPGA控制接口设计
蓝牙HCI―UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design
- 2022-07-10 22:33:51下载
- 积分:1
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SystemOfTaxiFeeBasedOnVerilogHDL
摘 要:以上海地区的出租车计费器为例,利用Verilog HDL语言设计了出租车计费器,使其具有时间
显示、计费以及模拟出租车启动、停止、复位等功能,并设置了动态扫描电路显示车费和对应时间,显示
了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优
化,下载到EPF1OK10TC144—3芯片中,可应用于实际的出租车收费系统。
关键词:Verilog HDL;电子自动化设计;硬件描述语言;MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)
- 2007-09-11 10:52:52下载
- 积分:1