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vhdl,无进位同步计数器，完成6进制加，输出6进制序列数
vhdl,无进位同步计数器，完成6进制加，输出6进制序列数-vhdl, non-binary synchronous counter to complete the six binary Canada, output 6, the number of binary sequences
- 2022-09-12 08:25:03下载
- 积分：1
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Am29LV160D
Am29LV160D数据基本知识手册，基本原理及工作方式。(Am29LV160D Data basic knowledge Manual, the basic principle and ways of working.)
- 2013-06-05 19:26:08下载
- 积分：1
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TEXTIO_Import_txt_Matlab
将FPGA设计仿真结果数据写入到txt记事本中，然后通过Matlab读取txt中的数据并显示图像(write the FPGA simulation result data into textbook,and read these data from textbook and display image in Matlab)
- 2012-12-28 13:42:57下载
- 积分：1
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paper_about_polypahse
一篇关于多相滤波器的论文,讲解了关于多信道的实现与仿真。(A paper about the polyphase filter，explained about the realization of multi-channel and simulation
)
- 2014-11-21 22:32:22下载
- 积分：1
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The code is used to interface PC monitor with Spartan 3E for the display. if you...
The code is used to interface PC monitor with Spartan 3E for the display. if you run the program on spartan 3 you would be able to see different test pattern on the monitor screen
- 2022-10-03 00:10:03下载
- 积分：1
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vhdl实现3*3矩阵乘法
矩阵乘法的vhdl实现，维数固定，很有启发性。着重了解接口，时序设定，延时控制。因为结构比较明晰，未添加stimulus文件，可以自行编写。
- 2022-03-20 17:34:43下载
- 积分：1
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vga
vga，显示彩条，及其简单易懂，适合初学(vga, display color bars, and its easy-to-understand, suitable for beginners)
- 2012-10-10 21:10:15下载
- 积分：1
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QC_LDPC译码器的FPGA设计
说明： LDPC码的FPGA实现，用verilog语言编写(FPGA implementation of LDPC code, written in Verilog language)
- 2019-11-15 06:04:33下载
- 积分：1
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vhdl testbentch 编写模板。非常实用
vhdl testbentch 编写模板。非常实用-vhdl testbentch prepared templates. Useful
- 2022-06-01 04:30:54下载
- 积分：1
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fir
用窗函数法设计一个线性相位FIR数字低通滤波器，用理想低通滤波器作为逼近滤波器，通带截止频率为0.2 ，阻带截止频率为0.4 ，阻带衰减不小于-40dB。(Window function method to design a linear phase FIR digital low-pass filter, as an ideal low-pass filter for approximation filter passband cutoff frequency of 0.2 stopband cutoff frequency of 0.4, the stop-band attenuation of less than-40dB.)
- 2012-09-24 13:54:07下载
- 积分：1
