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DE2_Default
基于DE2开发板的VGA显示模块，仅供大家参考(DE2 development board based on the VGA display module, for your reference)
- 2008-07-21 16:12:32下载
- 积分：1
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rs-decoder-make-byvhdl
- RS码是Reed-Solomon 码（理德－所罗门码）的简称，它是一类非二进制BCH码，在RS码中，输入信号分成k·m比特一组，每组包括k个符号，每个符号由m个比特组成。(- RS code is a Reed-Solomon code (Reed- Solomon codes) for short, is a non-binary BCH code, the RS code, the input signal is divided into a set of k · m bits, each including k symbols, each symbol consists of m bits.)
- 2021-04-28 15:58:44下载
- 积分：1
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10_ImageEdge
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)
- 2020-10-23 20:27:22下载
- 积分：1
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I2C
说明： iic总线挂接在amba的apb总线上，标准接口，verilog代码的实现(iic bus attached to the amba' s apb bus, standard interfaces, verilog code implementation)
- 2011-04-02 10:04:36下载
- 积分：1
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16C550-driver
C源碼16C550 串口驅動，使用中斷收送RS232資料(16C550 UART Driver)
- 2020-11-24 19:49:32下载
- 积分：1
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jitter_eliminate
verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏(verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots)
- 2009-11-24 15:51:44下载
- 积分：1
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pps_ketiao_rb2
说明： FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:02下载
- 积分：1
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verilog-digital-system-design-
verilog数字系统设计，一本很好的verilog学习的书籍，很适合初学者(verilog digital system design, a good verilog learning books, it is suitable for beginners)
- 2021-01-10 20:28:50下载
- 积分：1
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gmsk
说明： 利用fpga实现gmsk的调制并仿真，全部代码(Fpga implements gmsk)
- 2020-12-24 00:09:06下载
- 积分：1
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The_entire_FPGA_design_flow_Modelsim_Synplify
详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)
- 2009-04-06 10:12:48下载
- 积分：1
