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lab2
说明: 使用vivado和Xilinx开发板实现抢答器,开发板为Xilinx Artix-7(Using vivado and Xilinx development board to achieve the responder, the development board is Xilinx artix-7)
- 2021-04-23 01:58:48下载
- 积分:1
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fdivision
在quartus平台下,并使用verillog hdl编写的时钟分频仿真(In quartus platform and use verillog hdl write clock divider simulation)
- 2016-08-15 07:45:12下载
- 积分:1
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fifoi
基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码,深度可控(Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable)
- 2008-12-19 00:17:51下载
- 积分:1
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dw_ahb_dmac_db
It is Synopsys dmac controller databook
- 2020-10-10 10:27:34下载
- 积分:1
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read-string-from-FLASH
read data of type character from flash memory
- 2013-09-08 03:49:15下载
- 积分:1
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adder.ripple
an 16 bit ripple carry adder
- 2012-11-02 23:20:33下载
- 积分:1
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ov7670_sdram_vga_sobel
说明: 基于OV7670采集,SDRAM缓存,sobel处理,VGA显示的工程,内有全部代码,基于QUARTUS开发板实现。
FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board.
FPGA edge detection)
- 2019-04-23 17:31:00下载
- 积分:1
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psk_rician-channel-MATLAB
QPSK在赖斯信道下的模拟仿真,包括K=6和K=10下的情况(QPSK in, Laisi Xin Road, under the simulation, including the case of K = 6 and K = 10 under)
- 2013-04-26 21:30:18下载
- 积分:1
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APB 总线
APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
- 2017-08-22 16:04:06下载
- 积分:1
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pps_ketiao_rb2
FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:02下载
- 积分:1