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这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列...
这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列-This is a HDB3 encoder, can be transformed into an ordinary binary sequences in order to comply with the rules of HDB3 bipolar coding sequence
- 2022-12-15 13:45:03下载
- 积分：1
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用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0...
用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0
- 2023-04-12 03:05:04下载
- 积分：1
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adder
说明： 通过四个半加器的互联，来实现四位加法器的电路结构(Through the interconnection of four and a half adder to achieve the four adder circuit)
- 2011-02-20 15:17:15下载
- 积分：1
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业界标准的Verilog语法格式
verilog标准语法，还有很多的样例参考，学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)
- 2020-06-15 22:50:02下载
- 积分：1
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adder4
四位加法器 数码管显示 组合电路 verilog(adder4 smg display combitional circuit verilog)
- 2013-02-28 09:56:46下载
- 积分：1
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xilinx provided on the FPGA hardware design timing constraints of the amount of...
xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material
- 2023-06-26 19:00:04下载
- 积分：1
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motionjpeg的FPGA编码实现，有点老了，但是可以参考．有些东西和h.264是差不多的．...
motionjpeg的FPGA编码实现，有点老了，但是可以参考．有些东西和h.264是差不多的．-motionjpeg FPGA Coding, a bit old, but the reference. Some things and h.264 is roughly the same.
- 2022-04-30 02:44:38下载
- 积分：1
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本源码详细介绍了UART的经典实例，敬请下载，谢谢适用
本源码详细介绍了UART的经典实例，敬请下载，谢谢适用-The source described in detail a classic example of UART, please download, Thank you apply
- 2022-03-22 20:09:19下载
- 积分：1
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ag-overview
agilex fpga description
- 2019-05-13 18:21:04下载
- 积分：1
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TheResearchAndIPDesignOfSMBusBasedSmartBattery
本文研究了SMBus
规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下
(Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台
完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有
良好的性能。(This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.)
- 2009-03-26 12:16:53下载
- 积分：1
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