登录
首页 » VHDL » 这些是Verilog文件但我上传文本格式(记事本)

这些是Verilog文件但我上传文本格式(记事本)

于 2022-12-19 发布 文件大小:962.00 B
0 156
下载积分: 2 下载次数: 1

代码说明:

these are verilog files but i am uploading in text(notepad) format

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • sync-and-asyn_FIFO_verilog
    同步与异步FIFO的verilog实现,包括源代码,testbench,测试以及综合通过,还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)
    2021-03-07 14:19:29下载
    积分:1
  • sample_SPI
    这是一个瑞萨R78/G13的SPI演示程序,详细的放置了说明,很有用的源码(This is one of the SPI Renesas R78/G13 demonstration program, placed a detailed description of very useful source)
    2013-09-03 02:59:19下载
    积分:1
  • Two_Port_RAM_lab
    Actel双端口存储;通过串口发送数据初始化RAM,然后通过串口返回到上位机的串口调试程序显示(通过串口发送数据初始化RAM,然后通过串口返回到上位机的串口调试程序显示)
    2009-04-03 16:20:30下载
    积分:1
  • mig_7series_v1_9
    DDR3控制器源码,针对XilinxFPGA的DDR3控制器的源码,已经验证通过。(DDR3 Controller,complete DDR3 controll,have pass verificaion.)
    2016-08-16 09:27:43下载
    积分:1
  • abi123
    encoding and decoding of audio signal
    2013-02-02 18:59:16下载
    积分:1
  • verilog2000更新部分,请对照前一个标准。加入了一些新的支持
    verilog2000更新部分,请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support
    2022-02-04 06:03:56下载
    积分:1
  • 同步FIFO功能,通过Modelsim仿真Verilog语言描述6…
    同步FIFO功能,verilog语言描述,通过了modelsim 6.0 仿真,Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated
    2022-03-24 20:37:31下载
    积分:1
  • FPGA和DSP EMIFA口接口程序。在两FPGA分布
    FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.
    2023-01-25 08:30:04下载
    积分:1
  • 93 std
    -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
    2022-02-25 16:35:00下载
    积分:1
  • frame_syn
    2010-04-28 10:34:32下载
    积分:1
  • 696516资源总数
  • 106783会员总数
  • 25今日下载