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coasess.tar
register file in vhdl and alu
- 2009-12-24 15:03:08下载
- 积分：1
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24_Timer
说明： 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
- 2021-04-27 21:38:44下载
- 积分：1
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ComunicationRealizationBetweenFPGAandSerialInterfa
说明： 杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。
(杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.)
- 2008-11-18 15:41:34下载
- 积分：1
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vhdl学习程序
vhdl学习基本编写程序，关于温度的读取和显示，vhdl学习基本编写程序，关于温度的读取和显示，vhdl学习基本编写程序，关于温度的读取和显示
- 2022-02-03 11:27:12下载
- 积分：1
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The time of the year undergraduate graduate design, signal generator and frequen...
当年本科时的毕业设计，信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter
- 2023-08-01 18:30:02下载
- 积分：1
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AD4003_CTR
一个AD4003的测试/控制程序，2Ms/s，18bit的AD高速AD芯片(A AD4003 test / control program, 2Ms/s, 18bit AD high speed AD chip)
- 2020-08-24 08:18:16下载
- 积分：1
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交通灯的ＶＥＲＩＬＯＧ实现，含详细中文注释．
交通灯的ＶＥＲＩＬＯＧ实现，含详细中文注释．-Verilog realize traffic lights, with detailed notes in Chinese.
- 2022-05-15 02:49:07下载
- 积分：1
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ACO-OFDM
ACO-OFDM sdakldjas seuekdsjakdnskd
- 2021-04-13 22:58:55下载
- 积分：1
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RS-422standardmodulev2
rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)
- 2013-12-23 14:14:18下载
- 积分：1
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256M_sdram_OK
改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )
- 2013-12-23 16:15:43下载
- 积分：1
