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彩条产生程序 color_bar
说明： 彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)
- 2020-06-22 06:20:01下载
- 积分：1
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The use of FPGA to collect the new U.S. accelerometer data and the data collecte...
利用FPGA来采集美新加速度计的数据，并将FPGA采集到的数据传给ARM系统处理-The use of FPGA to collect the new U.S. accelerometer data and the data collected FPGA passed ARM system processing
- 2022-02-04 12:49:36下载
- 积分：1
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Sdram_Control_4Port
使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上(Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII)
- 2012-05-14 15:36:09下载
- 积分：1
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Code
提供了《自己动手写CPU》本书每一章涉及的OpenMIPS源代码、测试程序。(It provides the OpenMIPS source code and test program in each chapter, which is written in the book "do it yourself CPU".)
- 2020-07-01 23:00:02下载
- 积分：1
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new
说明： 通过spi实现加速度计adxl357读取xyz三轴方向的加速度值(Accelerometers adxl357 read the acceleration value of XYZ three-axis direction through SPI)
- 2021-03-23 08:49:15下载
- 积分：1
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3-8
3-8译码器，可以讲三位二进制输入转换为8中取1的输出信号(3-8 decoder, you can talk about the three binary input is converted to 8 of the output signal from 1)
- 2009-07-16 17:23:30下载
- 积分：1
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vgachar
VGA显示程序VHDL版本，适用于ALTERA的CPLD(VGA display program applies ALTERA CPLD)
- 2012-05-31 10:35:14下载
- 积分：1
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VHDL language used to achieve a display hours, minutes and seconds of the clock:...
用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.
- 2022-04-27 22:51:31下载
- 积分：1
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frame_syn
通信系统中数据的传输以帧为单位，在FPGA中帧头检测是通信系统中的一部分，该程序实现了FPGA中帧头的检测。(Transmission of data in a communication system in units of frames, the frame header is detected in the FPGA part of the communication system, the realization of the frame header is detected in the FPGA.)
- 2014-08-27 16:02:54下载
- 积分：1
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在ise10.1.3 Xilinx PicoBlaze的应用开发。
Xilinx PicoBlaze application developed in ISE10.1.3.
- 2023-07-28 07:25:03下载
- 积分：1
