随便写的很难看,希望大家给给建议和意见,现在想弄个别人的来参考一下。-Just write it is very difficult to see, I hope we have given to the suggestions and comments, and now want others to弄个reference.
关于verilog的各个基本模块的源代码,如加法器,寄存器,选择器及各个测试文件-With regard to the various basic modules Verilog source code, such as adders, registers, selectors and the various test file