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FPGA-DSP
vhdl编写的FPGA与DSP接口程序，在FPGA内分配了两块双BUFFER与DSP进行通信(vhdl prepared FPGA and DSP interface program, the FPGA within the allocated 2 pairs of BUFFER to communicate with the DSP)
- 2021-01-08 10:58:51下载
- 积分：1
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ADC0809 VHDL控制程序,基于VHDL语言，实现对ADC0809控制.
ADC0809 VHDL控制程序,基于VHDL语言，实现对ADC0809控制.-ADC0809 VHDL control procedures, based on the VHDL language, to achieve control of ADC0809.
- 2023-01-22 19:10:03下载
- 积分：1
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xapp1071
高速ADC及DAC接口的参考设计。在Xilinx FPGA上实现。(Reference design of xapp1071.)
- 2012-05-22 15:34:04下载
- 积分：1
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UART_real_time_clock
This is an UART real time clock
- 2009-06-07 01:21:41下载
- 积分：1
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此ip核是xvga视频接口控制器，主要针对xilinx公司的开发工具
此ip核是xvga视频接口控制器，主要针对xilinx公司的开发工具-This ip is nuclear XVGA video interface controller, the main target Xilinx
- 2022-01-25 16:44:58下载
- 积分：1
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gtwizard_254_127_ex_1113_3
说明： 配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
- 2019-06-17 21:33:56下载
- 积分：1
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hls_bluebook
非常好的catapult学习书, catabult 可用于高级综合，由c产生vhdl/verilog(very nice book for catabult study)
- 2011-08-18 16:15:08下载
- 积分：1
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sportswatch
完整的跑表设计，时，分，秒都显示，希望能对大家有用，谢啦(Complete stopwatch design, hours, minutes, seconds, show, hoping to be useful for everyone,)
- 2009-12-09 11:25:27下载
- 积分：1
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我的学习经验，一种自适应分频及分频方法的实现，很好用的哦...
我的学习经验，一种自适应分频及分频方法的实现，很好用的哦-my learning experience, an adaptive frequency-frequency method and the realization of the good, oh
- 2022-02-03 01:08:00下载
- 积分：1
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16 floating
16卫浮点FFT算法的VHDL实现，有测试文件。-16 floating-point FFT algorithm Wei VHDL realize, have the test paper.
- 2023-03-07 14:45:03下载
- 积分：1
