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8BIT_CPU
一个8位的CPU设计，用verilog语言写的，希望有用(A CPU OF 8 BITS
)
- 2020-07-01 09:00:02下载
- 积分：1
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freeDev数字应用开发板中的七段数码管的IP核的verilog实现
freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog
- 2022-01-31 19:57:07下载
- 积分：1
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429recive
实现FPGA接收429板卡发送的信号，并根据数据最后两位点亮相应的LED。(FPGA to achieve the 429 board to receive the signal sent, and according to the data of the last two of the corresponding LED.)
- 2015-11-26 11:18:19下载
- 积分：1
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myconstellation_final_2
bpsk qpsk 16qam 64qam的constellation(bpsk qpsk 16qam 64qam constellation)
- 2021-03-03 01:49:33下载
- 积分：1
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n_bit_counter
n bit generic shift registers
- 2011-03-18 17:55:19下载
- 积分：1
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RX_RS_DEC
OFDM系统新型RS编解码的verilogHDL设计，经测试误码率性能提高(OFDM system verilogHDL new RS codec design, improved bit error rate performance tested)
- 2020-12-31 10:59:00下载
- 积分：1
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SR_DDS
DDS信号源设计，有正弦波，方波，三角波，AM波，FM波，还有PSK,FSK,16QAM等多种信号产生。(DDS signal source design, there are sine, square wave, triangle wave, AM wave, FM wave, as well as PSK, FSK, 16QAM and other signal generation.)
- 2016-03-20 22:04:51下载
- 积分：1
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带LDN的的同步的预置数端子，并且带CLR的异步清零端
带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client
- 2022-02-22 00:30:35下载
- 积分：1
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有关FPGA芯片的管脚的封装的一些资料。
有关FPGA芯片的管脚的封装的一些资料。-Pin on the FPGA chip packaging some of the information.
- 2023-06-26 06:30:03下载
- 积分：1
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它执行浮点运算单元
it performs the floating point arithmetic unit
- 2022-08-09 12:14:10下载
- 积分：1
