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LowPassFilter
说明： 内部含3个模块，使用DDS产生200k与500k的正弦波，两者相加后过数字低通滤波（通带0-200k，阻带400k以上），并将波形输出，实测FFT分析中看不到500k分量。其中数字滤波器采用MATLAB设计（FIR+等波纹，阻带衰减-80dB）(There are three modules in the system. DDS is used to generate 200K and 500K sine waves. After adding the two modules, the digital low-pass filter (passband 0-200k, stopband above 400k) is used, and the waveform is output. 500K component can not be seen in the actual FFT analysis. The digital filter is designed by MATLAB (FIR + equal ripple, stopband attenuation - 80dB))
- 2020-09-09 14:21:01下载
- 积分：1
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edc_spi_command
单片机和FPGA的通信程序，发送5个数，传输稳定，可以自行修改可一次传多个数(MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pass)
- 2013-09-14 21:09:52下载
- 积分：1
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this is a verilog code about serial transmit receive.
this a verilog code about serial transmit receive.-this is a verilog code about serial transmit receive.
- 2022-11-29 07:45:03下载
- 积分：1
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detection of the following sequence ‘10110110’in VHDL
detection of the following sequence ‘10110110’in VHDL
- 2023-04-17 19:05:03下载
- 积分：1
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project_zy
超声波测距程序 适用传感器HC-SR04(The application of sensor HC-SR04 for ultrasonic range finder)
- 2017-12-25 18:05:12下载
- 积分：1
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用VHDL语言将二进制数据转换成十进制数据，并将十进制的每一个位分离出来单独存放。使用状态机实现，程序简单，仿真效果很理想，占用可编程器件的资源较少。...
用VHDL语言将二进制数据转换成十进制数据，并将十进制的每一个位分离出来单独存放。使用状态机实现，程序简单，仿真效果很理想，占用可编程器件的资源较少。-VHDL language with the binary data into decimal data and decimal places separated from each store individually. Realize the use of state machine, the program is simple, simulation results are satisfactory, occupation of programmable devices have fewer resources.
- 2023-03-27 15:30:04下载
- 积分：1
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pedometer
本文设计了基于加速度传感器的计步器，并通过仿真以及实际调试得到了相应的结果的记录。本实验首先通过加速度传感器检测目标物体的运动，产生脉冲，将脉冲放大后经过施密特触发器整型为方波，并给出了方波的调试电路图。然后编写程序，利用D触发器检测方波的上升沿，当上升沿到来时，计数，并对十位、个位分别编码，然后由使能信号交替控制数码管输出结果。本文给出了仿真以及调试的程序、结果。(This article is designed pedometer-based acceleration sensor and the corresponding results recorded by simulation and debugging. The experiments by first acceleration sensor detects the movement of the target object, generates a pulse, the pulse amplification is a square wave after the Schmitt trigger integer, and gives the the debug circuit diagram of a square wave. Then write procedures, the use of the rising edge of the detection of the square wave of the D flip-flop, when the rising edge, the count, and ten bits are encoded, and then alternately by the enable signal output of the digital control. In this paper, a simulation and debugging procedures, results.)
- 2013-03-13 08:58:22下载
- 积分：1
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应用VHDL语言将高稳晶振分频得到1pps，使用GPS的1pps信号作为触发...
应用VHDL语言将高稳晶振分频得到1pps，使用GPS的1pps信号作为触发-Application of VHDL language high stability crystal oscillator frequency to be 1pps, the use of GPS signals as a trigger of 1pps
- 2022-05-12 21:39:28下载
- 积分：1
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qianzhaowang
说明： 一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)
- 2019-01-21 17:18:13下载
- 积分：1
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Verilog digital system design tutorials, e
Verilog数字系统设计教程，作者夏宇闻电子书籍-Verilog digital system design tutorials, e-books by XIA Yu-Wen
- 2023-03-21 06:15:07下载
- 积分：1
