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改进的DCT算法设计，veriloghdl实现
改进的DCT算法设计，veriloghdl实现-Improved DCT algorithm design, veriloghdl realize
- 2022-03-07 20:38:18下载
- 积分：1
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PCI总线仲裁参考设计，Quicklogic提供的verilog代码
PCI总线仲裁参考设计，Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code
- 2022-03-11 02:19:45下载
- 积分：1
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3M
说明： 在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。(In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal generated by the M sequence generator, through the AD module on the oscilloscope display module, oil DA demodulation operation in the same block experiment board, the signal generation control LED lights off, and the modulated output signal displayed on the oscilloscope at the same time, and compared.)
- 2018-02-09 20:07:01下载
- 积分：1
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UART_FPGA
此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分，UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。(This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the baud clock external demand.)
- 2015-03-04 11:02:17下载
- 积分：1
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VHDL语言基本数学运算库
VHDL语言基本数学运算库-VHDL basic arithmetic library
- 2022-03-03 06:03:30下载
- 积分：1
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该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。...
该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.
- 2022-01-24 17:35:43下载
- 积分：1
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一些有用的PicoBlaze的来源。
Some useful PicoBlaze sources.
- 2022-01-26 02:08:20下载
- 积分：1
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基于MAX2运用Quartus实现串口通信
基于MAX2运用Quartus实现串口通信-MAX2-based use of Quartus Serial Communication
- 2022-04-09 03:43:20下载
- 积分：1
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AM-800480SBTMQW-TW0-pdf
800 x 480 / inch lcd
- 2013-01-15 21:43:46下载
- 积分：1
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pong_C5H
FPGA的经典例程，可以进行移植和借鉴使用(FPGA' s classic routines, can be transplanted and learn to use)
- 2011-07-23 10:15:41下载
- 积分：1
