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mission
基于FPGA和Matlab的均衡滤波器设计与实现
基于MATLAB的数字均衡器的设计
采用FPGA实现基于LMS算法的自适应均衡器的设计研究
PWM控制的FPGA实现
等众多与FPGA、MATLAB相关的滤波器和均衡器设计
( FPGA and MATLAB design of filter&EQ)
- 2016-04-03 12:37:42下载
- 积分：1
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EDA
Quatus下用Verilog语言编写的双向交通灯控制系统，内含程序及波形图，注释详细，课程设计(Verilog language Quatus two-way traffic light control system, containing program and waveforms, detailed annotations, curriculum design)
- 2021-01-09 12:58:51下载
- 积分：1
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Altera FIFO的多极级联，实现多个FIFO之间的数据传输。
Altera FIFO的多极级联，实现多个FIFO之间的数据传输。-Altera FIFO multi-polar cascading between multiple FIFO data transmission.
- 2022-03-17 08:34:07下载
- 积分：1
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breath
利用verilog写的PWM 程序，来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)
- 2020-06-17 04:40:01下载
- 积分：1
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xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。
xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。 -This simulation uses a AWGN module to include noise as part of the simulation. Prior to
running the simulation, the UniSim models for the encoder and decoder must be generated as
well as the AWGN module.
- 2022-02-03 00:45:18下载
- 积分：1
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电子时钟
基于DE2-115的数字时钟
1.液晶显示，数码管显示
2.整点报时
3.闹钟
4.设置时间
5.设置闹钟(Digital clock based on DE2-115
1. LCD display, digital tube display
2. whole point
3. alarm clock
4. setting time
5. set the alarm clock)
- 2021-03-06 23:39:29下载
- 积分：1
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waveform-generator-o-VHDL-program
实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波
--A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成
--各种波形的线形叠加输出。
(Achieve the four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output (square wave- A duty cycle is controlled), can store arbitrary waveform feature data and can to reproduce the waveform, it can perform- all kinds of linear superposition of the output waveform.)
- 2009-10-08 09:56:59下载
- 积分：1
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encoder_Z64_all_rate
Wimax矩阵的LDPC编码器，已通过modelsim仿真测试，并前在altera的FPGA板上通过测试,码率5/6，可进入代码内部修改参数，支持2/3,3/4其他2个码率，数据吞吐量为700M(Wimax based LDPC encoder, modelsim simulation passed, also passed on altera FPGA board, code rate 5/6, also support 2/3,3/4, throughout 700m)
- 2012-03-19 09:44:32下载
- 积分：1
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adder_array
adder_array的设计。加法器阵列设计，顶层模块，四步流水，21位(adder_array the design. The adder array design, top-level module, four-step pipeline, 21)
- 2013-04-17 00:19:05下载
- 积分：1
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pinlvji
用汇编语言设计的频率计，注释较详细，适于初学者学习使用(Assembly language design frequency meter, the comment in more detail, suitable for beginners to learn to use)
- 2012-04-16 10:47:59下载
- 积分：1
