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verilogCRC32
32位bit输入的CRC32校验,verilog的代码,以及modelsim的testbench代码(The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench)
- 2012-03-07 10:22:58下载
- 积分:1
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FIFO的verilog程序
动画电影好的颠覆活动符合大喊大吼,道光皇帝繁华的大喊大吼,给对方互动活动芳华虚度和。电饭锅很多新的,都会给读后心得黑灯瞎火大学,得到优惠电信用户读后心得颠覆活动消化道,颠覆活动符合东西方呼吸道,东方红乡读后心得银行信贷参加。
- 2022-01-24 09:57:06下载
- 积分:1
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shuzihongdianlu
数字钟电路的实现,可以24小时计时,可调整时间!(Digital clock circuit implementation, a 24-hour timer, adjustable time!)
- 2013-08-18 14:49:14下载
- 积分:1
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waveform_-generator
简易信号波形发生器,可以产生四种波形,频率1k-20K步进可调。学习Verilog HDL的好例子。(imple signal waveform generator, can produce four waveform, frequency 1 k-20 k step can be adjusted. Learning Verilog good example of HDL.
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- 2011-06-12 21:13:27下载
- 积分:1
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LCD1602
这是一个LCD1602底层驱动代码,TI公司LM3S系列的(This is a LCD1602 underlying driver code, TI company LM3S series)
- 2013-10-30 16:40:45下载
- 积分:1
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uart
Verilog UART is written in this file
- 2013-04-16 12:34:05下载
- 积分:1
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CAN
说明: ZYNQ中 PS 端 CAN接口的基本使用方法,并通过 CAN接口实现与 PC 端 CA N调试软件之间的数据接收和发送(The basic use method of PS end can interface in zynq, and the data receiving and sending with PC end can debugging software through can interface)
- 2020-04-03 16:41:52下载
- 积分:1
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adder16b
说明: 潘松那本书上用vhdl语言描述的16位并入并处加法器(Pan book vhdl language used to describe the 16-bit adder into his)
- 2009-07-23 17:02:22下载
- 积分:1
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tcd1209d
TCD1209D驱动程序
Verilog语言(TCD1209D driver Verilog language)
- 2021-04-08 09:49:01下载
- 积分:1
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FIR
FIR滤波器的VHDL源代码及测试文件,已通过编译仿真,绝对正确。(FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.)
- 2021-04-15 11:08:54下载
- 积分:1