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cnt24_t
这是二十四进制计数器的源程序，有需要的同学可以参照一下！(This is 24 hexadecimal counter source, needy students can refer to you!)
- 2008-12-22 09:29:29下载
- 积分：1
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Read_SPI_ADC
This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.
- 2015-10-13 14:43:13下载
- 积分：1
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cnt60
de2开发板上的一个小程序 模60的计数器/分频器(de2 board developed a small program module 60 of the counter/divider)
- 2011-11-28 20:28:12下载
- 积分：1
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LineBuffer仿真
在Verilog的编写中，IP核的调用会使项目的开发更加方便快捷，对于初学者来说，IP核调用很抽象，通过一个具体的简单的的例子可以使大家更清晰明了的理解IP核的调用，对Verilog的学习是有帮助的。
- 2022-12-06 13:50:04下载
- 积分：1
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dac5686
在FPGA上编写的通过SPI总线配置外部DAC芯片DAC5686的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 (Configure external DAC chip DAC5686 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀琀漀 SPI bus data format sent.)
- 2014-09-11 11:05:20下载
- 积分：1
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alarm
闹钟设计，VHDL，源代码。闹钟设计，VHDL，源代码。(Alarm clock design, VHDL, the source code.)
- 2011-05-23 18:30:29下载
- 积分：1
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6_Sets_of_8051_VHDL_Verilog
it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scripts, pdfs, netlists etc. and a MIPS IP package
- 2012-07-02 10:56:02下载
- 积分：1
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agc
无线通信中接收侧自动增益控制模块的vhdl代码实现(Receive side of the AGC module vhdl code for wireless communications)
- 2020-10-22 14:27:23下载
- 积分：1
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CPU_Project_board
CPU 5级流水线实现（加hazard处理与板级验证，板级验证带有按键消抖）(5-stage pipelined CPU (plus hazard dealing with board-level verification, board-level verification with key debounce))
- 2020-12-03 09:29:25下载
- 积分：1
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Gaussian Random number generator (hardware implemented)
This is hardware implemented Gaussian random number generator based on the article attached in the folder "Document"
The system is based on the Ziggurat Gaussin random algorithm and implemented when I was under-graduate.
Although it is not my original system, it is so helpful cause I can acquire a lot of useful skills of verilog programming such as pipeline.
It is well simulated on the synthesis tool (ISE14.7) and the printed data can be verified using Matlab which is in the "Document" folder.
The testbench fils is tb_Zigg.v, and the top module file is top_Zigg.v
Goodlucks~
- 2022-03-25 01:29:44下载
- 积分：1
