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CAN总线开发代码 can-sja1000
CAN总线开发代码，FPGA与sja1000通信，可实现CAN的接收和发送。(The FPGA and the sja1000 CAN bus development code, communication, which CAN realize the CAN send and receive.)
- 2021-04-14 17:08:55下载
- 积分：1
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uart代码
uart 串口 verilog 含testbench quartus工程 全双工 发送模块 接受模块
- 2022-04-07 03:03:29下载
- 积分：1
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FFT_verilog
说明： verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近(verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to)
- 2009-08-26 11:29:57下载
- 积分：1
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tb_modular
说明： Matlab to hdl code for Least_square testbench
- 2020-06-17 12:20:02下载
- 积分：1
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RS_Encode_Decode
RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)
- 2016-01-21 12:07:34下载
- 积分：1
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FPGA
FPGA项目开发实战讲解 [李宪强编著][电子工业出版社][2015.04][248页].pdf(FPGA Project Development combat explain [Li Xingjiang ed] [Electronic Industry Press] [2015.04] [248] .pdf)
- 2016-07-13 08:53:07下载
- 积分：1
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FPGASPI
FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)
- 2020-12-09 13:49:20下载
- 积分：1
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vhdl1008
PCI slave IP core, in VHDL language ,has been verified,it is very easy to use.
it is an ideal IP to study PCI,design PCI Bridge
- 2020-06-18 18:20:01下载
- 积分：1
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LS165
LS165移位寄存器的verilog语言编写(The writing of the Verilog language of LS165 shift register)
- 2020-11-22 22:59:34下载
- 积分：1
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16QAM
基于FPGA 16QAM解调verilog代码，(16QAMdemoluator veriliog)
- 2021-02-23 23:49:39下载
- 积分：1
