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Servo
VHDL servo control from
technique of Pulse Width Modulation (PWM )
- 2014-10-10 15:34:33下载
- 积分：1
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e_BIU
isa MEMORY PLAN eu biu asm
- 2020-06-25 19:20:02下载
- 积分：1
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performance with rayleigh
matlab bpsk with rayleigh performance expirement
- 2020-06-24 21:40:01下载
- 积分：1
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AMBA-Bus_Verilog_Model
说明： 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。(This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.)
- 2021-04-25 21:48:46下载
- 积分：1
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13.3_Tracing
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动跟踪(System Generator based image processing engineering, multimedia processing on FPGA source, video-based motion tracking)
- 2020-11-04 17:39:51下载
- 积分：1
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fir-filter
11阶fir数字滤波器的verilog程序设计，线性相位，系数量化处理(11 order of fir digital filter verilog programming, linear phase, the coefficient quantization)
- 2012-03-05 10:33:03下载
- 积分：1
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fm_parcial
this is a simulation fm in simulink mathlab this is one program with pll
- 2012-11-30 10:02:10下载
- 积分：1
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VHDL_example_100
本书通过100个实例，详细介绍便件描述语言vHDL的各种语法现象及其在专用集成电路(AHc)设计蝴还中的使用方法。(the book through one hundred examples, it detailed description language vHDL pieces of the phenomenon and its various grammatical in ASIC (AHc) were also designed butterfly The usage.)
- 2007-03-25 09:57:05下载
- 积分：1
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可编程波发生器
这是波发生器的顶层。它直接实例化 I/O 垫和实现设计所需的所有子模块。
- 2023-01-25 04:20:04下载
- 积分：1
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VLSIrtl_spi
说明： verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.(Verilog language to write the SPI interface, all synchronous design, low gate count. it is very easy to use embedded design programs.)
- 2021-05-13 13:30:02下载
- 积分：1
