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shift_split_data
关于一个串行数据输入 根据时序将数据分两路输出的程序 (on a serial data input timing will be based on output data using two procedures)
- 2006-07-04 09:40:55下载
- 积分:1
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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分:1
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tcdg
Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorithms existing, and I feel there is a need to understand how they work. So this text explains a number of popular encryption algorithms and makes you look at them as mathematical formulas.
- 2014-01-29 15:57:35下载
- 积分:1
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Coding Style
说明: 良好的Coding Style能减少Bug,减少锁存器出现的可能以及其他隐藏逻辑错误,也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)
- 2020-06-17 12:00:01下载
- 积分:1
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SystemVerilog验证++测试平台编写指南
说明: 基于sv的uvm平台搭建实战,对于验证方法学来说,分层的测试平台是一个关键的概念。虽然分层似乎会使测试平台变得更复杂,但它能够把代码分而治之,有助于减轻工作负担,而且重复利用效率提升。验证平台可以类似分为五个层次:信号层、命令层、功能层、场景层和测试层。(Construction of UVM platform based on SV)
- 2020-07-19 16:18:46下载
- 积分:1
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vhdl
vhdl常见小实验代码,包括二进制比较器,4选1,8421十进制,8421转化成格雷码,8421余三码,分频器,数据码译码器,二进制减计数器,四位环形计数器等(VHDL common small experiment code)
- 2020-06-24 13:00:02下载
- 积分:1
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CPLD_DEMO_OK
可以给VHDL初学者看的实例,全部经过验证(VHDL beginners can see examples of all the proven)
- 2011-01-12 21:09:45下载
- 积分:1
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circuit_timing
verilog延时电路的不同写法,和综合能否。可对比学习(Different wording verilog delay circuit, and comprehensive ability. Comparable learning)
- 2014-05-14 18:02:44下载
- 积分:1
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A Microchip PIC-Compatible RISC CPU IP Core Design and Verilog Implementation
A Microchip PIC-Compatible RISC CPU IP Core Design and Verilog Implementation
含Verilog源代码以及设计文档
本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码,当然有一些模块是在quartus中直接编辑波形测试的,所以没有响应的测试脚本文件。
tri_state_port的测试还未完成,test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务
其中有三篇文档:
PIC10_RISC_Design.pdf:原文(verilog代码基本都来自原文,对一部分进行了改进),这篇文章写得非常好
PIC10F200_单片机IP核的实现.pdf:对上面的文章结合自己的实验过程进行了翻译和改写,给大家参考
PIC10F:PIC10系列单片机的手册
- 2022-01-25 19:42:36下载
- 积分:1
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VHDLFIR
1 由matlab计算FIR数字滤波器的滤波系数;
2 用VHDL语言设计逻辑电路,再通过QUARTUS II 软件,将各个模块的电路封装成期间,在顶层设计中通过连线,完成整个系统。
(matlab
VHDL
QUARTUS )
- 2016-05-15 12:49:30下载
- 积分:1